Pre-computation of memory core control signals

ABSTRACT

An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

CLAIM OF PRIORITY

This application is a continuation application of U.S. patentapplication Ser. No. 16/810,243, entitled “PRE-COMPUTATION OF MEMORYCORE CONTROL SIGNALS,” by Zhang et al., filed Mar. 5, 2020 andincorporated herein by reference in its entirety.

BACKGROUND

Semiconductor memory is widely used in various electronic devices suchas cellular telephones, digital cameras, personal digital assistants,medical electronics, mobile computing devices, servers, solid statedrives, non-mobile computing devices and other devices. Semiconductormemory may comprise non-volatile memory or volatile memory. Anon-volatile memory allows information to be stored and retained evenwhen the non-volatile memory is not connected to a source of power(e.g., a battery).

BRIEF DESCRIPTION OF THE DRAWINGS

Like-numbered elements refer to common components in the differentfigures.

FIG. 1 is a functional block diagram of a memory device.

FIG. 1A is a block diagram depicting one example of a memory structure.

FIG. 1B is a block diagram depicting one embodiment of the sense blockSB1 of FIG. 1A.

FIG. 2 is a block diagram depicting one embodiment of a memory system.

FIG. 3 depicts an embodiment of circuits for applying voltages to amemory structure.

FIG. 4 depicts threshold voltage distributions.

FIG. 5 is a flow chart describing one embodiment of a process forprogramming/writing data into memory cells connected to a common wordline.

FIG. 6 is a flowchart of one embodiment details of programmingnon-volatile storage during step 572 of FIG. 5.

FIG. 7 shows timing of various signals during one embodiment of theprocess of FIG. 6.

FIG. 8 is a high-level block diagram of one embodiment of amicrocontroller, having three processors, and other elements.

FIG. 9 is a block diagram of one embodiment of a microcontrollerconfigured to issue core timing control (CTC) signals.

FIG. 10A is a diagram that shows how a CTC signal may be used to controla voltage waveform during an embodiment of a memory operation.

FIG. 10B depicts one embodiment of master table pertaining to CTCsignals.

FIG. 11A illustrates an embodiment of a packet that contains informationthat may be used by the MCU to generate one or more CTC signals.

FIG. 11B illustrates an embodiment of a packet that contains informationthat may be used to cache information for generating one or more CTCsignals.

FIG. 12 depicts a flowchart of one embodiment of a process of generatingCTC signals for a memory operation or segment thereof.

FIGS. 13A-13D depict flowcharts of several different embodiments ofgenerating CTC signals.

FIG. 14A is a flowchart of one embodiment of a command level flow forthe Sequence Processor.

FIG. 14B is a flowchart of one embodiment of a process of executing acommand on Sequence Processor.

FIG. 14C is a flowchart of one embodiment of a sub-clock flow performedby Sequence Processor.

FIG. 15 is a flowchart of one embodiment of a process of processing apacket in order to generate CTC signals.

DETAILED DESCRIPTION

A proposed non-volatile memory system includes a memory structure and acontrol circuit connected to the memory structure. The memory structureincludes non-volatile memory cells. The control circuit may include aprogrammable and reprogrammable microcontroller (e.g., MCU), in anembodiment. In one embodiment, the microcontroller is configured tooutput Core Timing Control (CTC) signals. The CTC signals are used tocontrol voltages that are applied in the memory structure to controlmemory operations such as program, read, and erase. The CTC signals mayalso be referred to as memory core control signals. In one embodiment,the MCU sets or resets CTC signals during a memory operation in order tocontrol the voltages. For example, the CTC signals may be used tocontrol the timing of voltages applied to word lines, bit lines, selectlines, and other elements or control lines in the memory structure. TheMCU is used in a bit-cost-scalable (BiCs) architecture, in someembodiments.

A memory operation may contain multiple segments, which are referred toherein as sub-clocks. In some embodiments, a CTC signal may either beset or reset during a sub-clock. When a CTC signal is set, acorresponding voltage that is applied to the memory structure mayincrease from, for example, low to high. In some embodiments, the MCUdetermines the low and high voltages. When a CTC signal is reset, thecorresponding voltage may decrease from high to low.

Computing the CTC signals using a processor in the MCU may requirenumerous processor clock cycles. For example, computing the CTC signalscould include a first step of computing conditions that may be based ona combination of modes (or sub-modes), parameters, and/or statedependent bits. An example of a mode is a read, write or erase command.Examples of sub-modes for a read command include a multi-bit per cellread (MLC read) and a single-bit per cell read (SLC read). Theparameters may be used to specify various options that can be appliedduring a memory command. A state dependent bit may define how the flowof the CTC signals is to proceed. For example, a state dependent bitcould indicate that a wait state is needed at a certain point. In oneembodiment, a condition is a combinational logic clause with inputs frommodes, sub-modes, parameters, and/or state dependent bits. The conditionis not limited to these inputs. In some embodiments, the conditions aredetermined for each sub-clock of a memory operation.

Determining the CTC signals may include a second step of determining theCTC signals based on the conditions. For some memory operations (orsegments thereof), it may be acceptable to take numerous processor clockcycles to compute the CTC signals. However, for other memory operations(or segments thereof) it may be desirable to have a faster way togenerate the CTC signals. One possible solution to generate theaforementioned conditions, as well as the CTC signals, is to usecombinational logic. Combinational logic can be faster than a processor.However, combinational logic is not as flexible as a processor. Forexample, changing the combinational logic may be achieved by modifyingmetal layers in silicon. Embodiments that have programmable andreprogrammable MCU to generate the CTC signals provide flexibility inthat changes can be made to the CTC signals using updates toinstructions and/or parameters used by the processor.

In one embodiment, information from which the CTC signals may bedirectly generated is pre-computed and stored. For example, set/resetinformation that specifies when voltages to be applied to thenon-volatile memory structure are to be set or reset may be pre-computedand stored. This pre-computation may be performed in a power on phase ofthe memory system, but may also be performed after power on. When arequest to perform a memory operation of that type is received, thestored set/reset information may be accessed and used to generate theCTC signals to control the memory operation. Thus, considerable time issaved. Note that this time savings occurs each time a memory operationof the type is performed. Also, power is saved due to not having torepeatedly perform the computation. Moreover, because the set/resetinformation is computed, it is possible to modify the CTC signals byaltering parameters or instructions used to perform the computation.

Storing the set/reset information may require a significant amount ofstorage. In one embodiment, rather than pre-computing the set/resetinformation, various conditions discussed above are pre-computed andstored. When a request to perform a memory operation of is received, thestored conditions may be accessed and used to generate the CTC signals.Thus, considerable time is saved by not having to determine theconditions at run time (when a request to perform the memory operationis received). Note that this time savings occurs each time a memoryoperation is performed. Also, power is saved due to not having torepeatedly perform the computation. Moreover, because the conditions arecomputed, it is possible to modify the conditions and hence the CTCsignals by altering parameters or instructions used to perform thecomputation.

As noted above, a memory operation may contain multiple segments, whichare referred to herein as sub-clocks. In some embodiments, thepre-computation is performed for a particular sub-clock of a memoryoperation. A reason for this is that there may be a limited amount oftime prior to the sub-clock in order to perform the computation. If thecomputation were to be performed at run time, the computation couldresult in a need to add an unnecessary delay to memory operation inorder to generate the CTC signals for a sub-clock.

FIGS. 1-3 describe one set of examples of a memory system that can beused to implement the technology described herein. FIG. 1 is afunctional block diagram of an example memory system 100. The componentsdepicted in FIG. 1 are electrical circuits. Memory system 100 includesone or more memory die 108. The one or more memory die 108 can becomplete memory die or partial memory die.

In one embodiment, each memory die 108 includes a memory structure 126,control circuitry 110, and read/write circuits 128. Memory structure 126is addressable by word lines via a row decoder 124 and by bit lines viaa column decoder 132. Read/write circuits 128 include multiple senseblocks 150 including SB1, SB2, . . . , SBp (sensing circuitry) and allowa page of memory cells to be read or programmed in parallel.

In some systems, a controller 122 is included in the same package (e.g.,a removable storage card) as the one or more memory die 108. However, inother systems, controller 122 can be separated from memory die 108. Insome embodiments controller 122 will be on a different die than thememory die 108. In some embodiments, a single controller 122 willcommunicate with multiple memory die 108. In other embodiments, eachmemory die 108 has its own controller. Commands and data are transferredbetween a host 140 and controller 122 via a data bus 120, and betweencontroller 122 and the one or more memory die 108 via lines 118. In oneembodiment, memory die 108 includes a set of input and/or output (I/O)pins that connect to lines 118.

Control circuitry 110 cooperates with the read/write circuits 128 toperform memory operations (e.g., write, read, and others) on memorystructure 126, and includes a programmable and reprogrammablemicrocontroller (MCU) 112, an on-chip address decoder 114, and a powercontrol circuit 116. Microcontroller 112 provides die-level control ofmemory operations. In an embodiment, microcontroller 112 is programmableby software. In other embodiments, microcontroller 112 does not usesoftware and is completely implemented in hardware (e.g., electricalcircuits).

In an embodiment, control circuitry 110 includes buffers 130 such asregisters, ROM fuses and other storage devices for storing defaultvalues such as base voltages and other parameters. In one embodiment,the default values are stored in memory structure 126. In oneembodiment, the default values are loaded from memory structure intobuffers 126 during a power on phase. In one embodiment, the MCU 112accesses the default values during the power on phase, and pre-computesinformation for generating CTC signals for a type of memory operation.For example, the type of memory operation could be an MLC read or an SLCread. However, the type of memory operation is not limited to a readoperation. The MCU 112 stores the pre-computed information in, forexample, latches in the MCU 112. Thus, the MCU 112 need not compute theinformation each time that the type of memory operation is executed.

On-chip address decoder 114 provides an address interface betweenaddresses used by host 140 or controller 122 to the hardware addressused by row decoder 124 and column decoder 132. Power control circuit116 controls the power and voltages supplied to the word lines and bitlines during memory operations. Power control circuit 116 may includecharge pumps for creating voltages. Sense blocks 150 include bit linedrivers.

Microcontroller 112 and/or controller 122 (or equivalently functionedcircuits), in combination with all or a subset of the other circuitsdepicted in FIG. 1, can be considered to be one or more control circuitsthat performs the functions described herein. The one or more controlcircuits can include hardware only or a combination of hardware andsoftware (including firmware). For example, a controller programmed byfirmware to perform the functions described herein is one example of acontrol circuit. The one or more control circuits can include aprocessor, Field Programmable Gate Array (FPGA), Application SpecificIntegrated Circuit (ASIC), integrated circuit or other type of circuit.

In an embodiment, control circuitry 110 (including microcontroller 112),read/write circuits 128, decoders 124 and decoders 132 are positioned onthe substrate and underneath memory structure 126, which may be referredto as a “circuit under array.”

Controller 122 (which in one embodiment is an electrical circuit) mayinclude one or more processors 122 c, ROM 122 a, RAM 122 b, a memoryinterface (MI) 122 d and a host interface (HI) 122 e, all of which areinterconnected. The storage devices (ROM 122 a, RAM 122 b) store code(software) such as a set of instructions (including firmware), and oneor more processors 122 c is/are operable to execute the set ofinstructions to provide the functionality described herein.Alternatively or additionally, one or more processors 122 c can accesscode from a storage device in memory structure 126, such as a reservedarea of memory cells connected to one or more word lines. RAM 122 b canbe to store data for controller 122, including caching program data(discussed below).

Memory interface 122 d, in communication with ROM 122 a, RAM 122 b andprocessor 122 c, is an electrical circuit that provides an electricalinterface between controller 122 and one or more memory die 108. Forexample, memory interface 122 d can change the format or timing ofsignals, provide a buffer, isolate from surges, latch I/O, etc. One ormore processors 122 c can issue commands to control circuitry 110 (oranother component of memory die 108) via Memory Interface 122 d. Hostinterface 122 e provides an electrical interface with host 140 via databus 120 to receive commands, addresses and/or data from host 140 toprovide data and/or status to host 140.

In one embodiment, memory structure 126 includes a three-dimensional(3D) memory array of non-volatile memory cells in which multiple memorylevels are formed above a substrate, such as a wafer. Memory structure126 (which may be referred to as a “non-volatile memory structure”) mayinclude any type of non-volatile memory that are monolithically formedin one or more physical levels of arrays of memory cells having anactive area disposed above a silicon (or other type of) substrate. Inone example, the non-volatile memory cells comprise vertical NANDstrings with charge-trapping material.

In another embodiment, memory structure 126 includes a two-dimensional(2D) memory array of non-volatile memory cells. In one example, thenon-volatile memory cells are NAND flash memory cells utilizing floatinggates. Other types of memory cells (e.g., NOR-type flash memory) alsocan be used.

The exact type of memory array architecture or memory cell included inmemory structure 126 is not limited to the examples above. Manydifferent types of memory array architectures or memory technologies canbe used to form memory structure 126. No particular non-volatile memorytechnology is required for purposes of the new claimed embodimentsproposed herein. Other examples of suitable technologies for memorycells of memory structure 126 include ReRAM memories, magnetoresistivememory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM),phase change memory (e.g., PCM), and the like. Examples of suitabletechnologies for memory cell architectures of memory structure 126include two dimensional arrays, three dimensional arrays, cross-pointarrays, stacked two dimensional arrays, vertical bit line arrays, andthe like.

One example of a ReRAM, or PCMRAM, cross point memory includesreversible resistance-switching elements arranged in cross point arraysaccessed by X lines and Y lines (e.g., word lines and bit lines). Inanother embodiment, the memory cells may include conductive bridgememory elements. A conductive bridge memory element also may be referredto as a programmable metallization cell. A conductive bridge memoryelement may be used as a state change element based on the physicalrelocation of ions within a solid electrolyte. In some cases, aconductive bridge memory element may include two solid metal electrodes,one relatively inert (e.g., tungsten) and the other electrochemicallyactive (e.g., silver or copper), with a thin film of the solidelectrolyte between the two electrodes. As temperature increases, themobility of the ions also increases causing the programming thresholdfor the conductive bridge memory cell to decrease. Thus, the conductivebridge memory element may have a wide range of programming thresholdsover temperature.

Magnetoresistive memory (MRAM) stores data by magnetic storage elements.The elements are formed from two ferromagnetic plates, each of which canhold a magnetization, separated by a thin insulating layer. One of thetwo plates is a permanent magnet set to a particular polarity; the otherplate's magnetization can be changed to match that of an external fieldto store memory. A memory device is built from a grid of such memorycells. In one embodiment for programming, each memory cell lies betweena pair of write lines arranged at right angles to each other, parallelto the cell, one above and one below the cell. When current is passedthrough them, an induced magnetic field is created.

Phase change memory (PCM) exploits the unique behavior of chalcogenideglass. One embodiment uses a GeTe—Sb₂Te₃ super lattice to achievenon-thermal phase changes by simply changing the co-ordination state ofthe Germanium atoms with a laser pulse (or light pulse from anothersource). Therefore, the doses of programming are laser pulses. Thememory cells can be inhibited by blocking the memory cells fromreceiving the light. Note that the use of “pulse” in this document doesnot require a square pulse, but includes a (continuous ornon-continuous) vibration or burst of sound, current, voltage light, orother wave.

A person of ordinary skill in the art will recognize that the technologydescribed herein is not limited to a single specific memory structure,but covers many relevant memory structures within the spirit and scopeof the technology as described herein and as understood by one ofordinary skill in the art.

FIG. 1A depicts an example of memory structure 126. In one embodiment,an array of memory cells is divided into multiple planes. In the exampleof FIG. 1A, memory structure 126 is divided into two planes: plane 141and plane 143. In other embodiments, more or less than two planes can beused. In some embodiments, each plane is divided into a number of memoryerase blocks (e.g., blocks 0-823, or another amount).

In certain memory technologies (e.g., 2D/3D NAND and other types offlash memory), a memory erase block is the smallest unit of memory cellsfor an erase operation. That is, each erase block contains the minimumnumber of memory cells that are erased together in a single eraseoperation. Other units of erase also can be used. In other memorytechnologies (e.g., MRAM, PCM, etc.) used in other embodimentsimplementing the solution claimed herein, memory cells may beoverwritten without an erase operation and so erase blocks may notexist.

Each memory erase block includes many memory cells. The design, size,and organization of a memory erase block depends on the architecture anddesign for the memory structure 126. As used herein, a memory eraseblock is a contiguous set of memory cells that share word lines and bitlines. For example, erase block i of FIG. 1A includes memory cells thatshare word lines WL0_i, WL1_i, WL2_i and WL3_i and share bit linesBL0-BL69,623.

In one embodiment, a memory erase block (see block i) contains a set ofNAND strings which are accessed via bit lines (e.g., bit linesBL0-BL69,623) and word lines (WL0, WL1, WL2, WL3). FIG. 1A shows fourmemory cells connected in series to form a NAND string. Although fourcells are depicted to be included in each NAND string, more or less thanfour can be used (e.g., 16, 32, 64, 128, 256 or another number or memorycells can be on a NAND string). One terminal of the NAND string isconnected to a corresponding bit line via a drain select gate, andanother terminal is connected to the source line via a source selectgate. Although FIG. 1A shows 69624 bit lines, a different number of bitlines also can be used.

Each memory erase block and/or each memory storage unit is typicallydivided into a number of pages. In one embodiment, a page is a unit ofprogramming/writing and a unit of reading. Other units of programmingcan also be used. One or more pages of data are typically stored in onerow of memory cells. For example, one or more pages of data may bestored in memory cells connected to a common word line. A page includesuser data and overhead data (also called system data). Overhead datatypically includes header information and Error Correction Codes (ECC)that have been calculated from the user data of the sector. Thecontroller (or other component) calculates the ECC when data are beingwritten into the array, and also checks the ECC when data are being readfrom the array. In one embodiment, a page includes data stored in allmemory cells connected to a common word line.

In the example discussed above, the unit of erase is a memory eraseblock and the unit of programming and reading is a page. Other units ofoperation also can be used. Data can be stored/written/programmed, reador erased a byte at a time, 1K bytes, 512K bytes, etc. No particularunit of operation is required for the claimed solutions describedherein. In some examples, the system programs, erases, and reads at thesame unit of operation. In other embodiments, the system programs,erases, and reads at different units of operation. In some examples, thesystem programs/writes and erases, while in other examples the systemonly needs to program/write, without the need to erase, because thesystem can program/write zeros and ones (or other data values) and canthus overwrite previously stored information.

As used herein, a memory storage unit is the set of memory cellsrepresenting the smallest storage unit of operation for the memorytechnology to store/write/program data in to the memory structure 126.For example, in one embodiment, the memory storage unit is a page sizedto hold 4 KB of data. In certain embodiments, a complete memory storageunit is sized to match the number of physical memory cells across a rowof the memory structure 126. In one embodiment, an incomplete memorystorage unit has fewer physical memory cells than a complete memorystorage unit.

FIG. 1B is a block diagram depicting one embodiment of the sense blockSB1 of FIG. 1. Sense block SB1 is partitioned into one or more coreportions, referred to as sense modules (e.g., SM0) or sense amplifiers,and a common portion, referred to as a managing circuit (e.g., MC0). Inone embodiment, there is a separate sense module for each bit line andone common managing circuit for a set of sense modules, such as SM0,SM1, SM2 and SM3. Each of the sense modules in a group communicates withthe associated managing circuit via a data bus 172. Thus, there are oneor more managing circuits which communicate with the sense modules of aset of memory cells.

Each sense module SM0, SM1, SM2 and SM3 includes sense circuitry SC0,SC1, SC2 and SC3, respectively, that performs sensing by determiningwhether a conduction current in a connected bit line BL0, BL1, BL2 andBL3, respectively, is above or below a predetermined threshold voltage(verify voltage). Each sense module SM0, SM1, SM2 and SM3 also includesa bit line latch BLL0, BLL1, BLL2 and BLL3, respectively, that is usedto set a voltage condition on the connected bit line. For example,during a programming operation, a predetermined state latched in a bitline latch will result in the connected bit line being pulled to alockout state (e.g., 1.5-3 V), a slow programming state (e.g., 0.5-1 V)or a normal programming state (e.g., 0 V).

Managing circuit MC0 includes a data latch processor 192, four examplesets of data latches 194(0), 194(1), 194(2) and 194(3) and an I/Ointerface 198 coupled between the sets of data latches 194 and lines118. In this example, each set of latches is associated with one of thebit lines. For example, data latches 194(0) are associated with bit lineBL0, data latches 194(1) are associated with bit line BL1, data latches194(2) are associated with bit line BL2, and data latches 194(3) areassociated with bit line BL3.

Each set of data latches includes data latches identified by LDL 151,MDL 152, and UDL 153, in this embodiment. LDL 151 stores a bit for alower page of write data, MDL 152 stores a bit for a middle page ofwrite data, and UDL 153 stores a bit for an upper page of write data, ina memory which stores three bits of data in each memory cell. Note thatthere may be one set of such latches associated with each bit line. Thelatches 194 also may be used to store data read from the non-volatilememory cells.

Additional or fewer data latches per set could be used as well. Forexample, in a two-bit per memory cell implementation, the MDL data latchfor the middle page of data is not needed. A four-bit per memory cellimplementation can use LDL, LMDL (lower-middle page), UMDL (upper-middlepage), and UDL latches. The techniques provided herein are meant toencompass such variations. In a further option, another latch is used toidentify whether a memory cell is in a slow programming mode when itsthreshold voltage is within a specified margin of the verify voltage ofits target data state.

Data latch processor 192 performs computations during reading andprogramming. For reading, data latch processor 192 determines the datastate stored in the sensed memory cell and stores the data in the set ofdata latches. For full programming and refresh programming, data latchprocessor 192 reads the latches to determine the data state which is tobe written to a memory cell.

During reading, the operation of the system is under the control ofmicrocontroller 112 which controls the supply of different control gatevoltages to the addressed memory cell. As it steps through the variouspredefined control gate voltages corresponding to the various memorystates supported by the memory, the sense module may trip at one ofthese voltages and a corresponding output will be provided from thesense module to data latch processor 192 via data bus 172. At thatpoint, data latch processor 192 determines the memory state byconsidering the tripping event(s) of the sense module and theinformation about the applied control gate voltage from microcontroller112 via input lines 193.

Data latch processor 192 then computes a binary encoding for the memorystate and stores the resultant data bits into the data latches 194. Forexample, the memory state for a memory cell associated with bit line BL0may be stored in latches 194(0), etc. Herein, a “memory state” may alsobe referred to as a “data state.” In another embodiment of the managingcircuit MC0, the bit line latch serves both as a latch for latching theoutput of the sense module and also as a bit line latch as describedabove.

In an embodiment, MCU 112 executes instructions to control data latchprocessor 192 to test conditions of non-volatile memory cells inresponse to voltages applied to memory structure 126 (such as referencevoltages applied to the non-volatile memory cells). The condition of anon-volatile memory cell can be any physical parameter of a non-volatilememory cell. Example conditions include, but are not limited to, a datastate (e.g., S0-S7 in FIG. 4), a conduction current, a resistance, and atransistor threshold voltage. The manner in which the condition may betested may include, but is not limited to, sensing, reading, detecting,measuring, probing, discovering, discriminating, checking, examining,and determining.

In an embodiment, MCU 112 executes instructions to control data latchprocessor 192 to determine a data state (e.g., S0-S7 in FIG. 4) ofmemory cells. The data state may be defined by a range of some physicalparameter including, but not limited to, transistor threshold voltage,resistance, or current. Thus, to determine a data state means todetermine what range of a certain physical parameter a memory cell isin.

In an embodiment, MCU 112 executes instructions to control data latchprocessor 192 to determine whether a memory cell conducts a current inresponse to voltages applied to the memory cell. In an embodiment, MCU112 executes instructions to control data latch processor 192 todetermine whether the threshold voltage of a memory cell is above orbelow a reference voltage (e.g., Vr1-Vr7; or Vv1-Vv7 in FIG. 4) appliedto the memory cell.

Some implementations can include multiple processors. In one embodiment,each processor will include an output line (not depicted) such that eachof the output lines is wired-OR'd together. In some embodiments, theoutput lines are inverted prior to being connected to the wired-OR line.This configuration enables a quick determination during the programverification process of when the programming process has completedbecause microcontroller 112 receiving the wired-OR can determine whenall bits being programmed have reached the desired level.

For example, when each bit has reached its desired level, a logic zerofor that bit will be sent to the wired-OR line (or a data one isinverted). When all bits output a data 0 (or a data one inverted), thenmicrocontroller 112 knows to terminate the programming process. Becauseeach processor communicates with four sense modules, microcontroller 112needs to read the wired-OR line four times, or logic is added to datalatch processor 192 to accumulate the results of the associated bitlines such that microcontroller 112 need only read the wired-OR line onetime. Similarly, by choosing the logic levels correctly, microcontroller112 can detect when the first bit changes its state and change thealgorithms accordingly.

During program or verify operations, the data to be programmed (writedata) are stored in data latches 194 from lines 118, in the LDL, MDL,and UDL data latches. For example, the data to be programmed in aselected memory cell associated with bit line BL0 may be stored inlatches 194(0), the data to be programmed in a selected memory cellassociated with bit line BL1 may be stored in latches 194(1), etc. Theprogramming operation, under the control of microcontroller 112,comprises a series of programming voltage pulses applied to the controlgates of the addressed memory cells. Each programming voltage isfollowed by a read back (verify test) to determine if the memory cellhas been programmed to the desired memory state.

In some cases, data latch processor 192 monitors the read back memorystate relative to the desired memory state. When the two states agree,data latch processor 192 sets the bit line latch to cause the bit lineto be pulled to a state designating program inhibit (e.g., 2-3V). Thisinhibits the memory cell coupled to the bit line from furtherprogramming even if programming voltages appear on its control gate. Inother embodiments, data latch processor 192 initially loads the bit linelatch, and the sense circuitry sets the bit line latch to an inhibitvalue during the verify process.

Each set of data latches 194 may be implemented as a stack of datalatches for each sense module. In some implementations, the data latchesare implemented as a shift register so that the parallel data storedtherein is converted to serial data for lines 118, and vice versa. Allthe data latches corresponding to the read/write block of memory cellscan be linked together to form a block shift register so that a block ofdata can be input or output by serial transfer. In particular, the bankof read/write modules is adapted so that each of its set of data latcheswill shift data in to or out of the data bus in sequence as if they arepart of a shift register for the entire read/write block.

FIG. 2 is a block diagram of example memory system 100, depicting moredetails of one embodiment of controller 122. In an embodiment,controller 122 is a flash memory controller. Non-volatile memory 108 isnot limited to flash memory technology. Thus, controller 122 is notlimited to the example of a flash memory controller. As used herein, aflash memory controller is a device that manages data stored in flashmemory and communicates with a host, such as a computer or electronicdevice. A flash memory controller can have various functionality inaddition to the specific functionality described herein. For example, aflash memory controller can format the flash memory to ensure the memoryis operating properly, map out bad flash memory cells, and allocatespare memory cells to be substituted for future failed cells. Some partof the spare cells can be used to hold firmware to operate the flashmemory controller and implement other features.

In operation, when a host needs to read data from or write data to theflash memory, the host will communicate with the flash memorycontroller. If the host provides a logical address to which data are tobe read/written, the flash memory controller can convert the logicaladdress received from the host to a physical address in the flashmemory. (Alternatively, the host can provide the physical address). Theflash memory controller also can perform various memory managementfunctions, such as, but not limited to, wear leveling (distributingwrites to avoid wearing out specific blocks of memory that wouldotherwise be repeatedly written to) and garbage collection (after ablock is full, moving only the valid pages of data to a new block, sothe full block can be erased and reused).

The interface between controller 122 and non-volatile memory die 108 maybe any suitable flash interface, such as Toggle Mode 200, 400, or 800.In one embodiment, memory system 100 may be a card based system, such asa secure digital (SD) or a micro secure digital (micro-SD) card. In analternate embodiment, memory system 100 may be part of an embeddedmemory system. For example, the flash memory may be embedded within thehost. In other example, memory system 100 can be in the form of a solidstate drive (SSD).

In some embodiments, non-volatile memory system 100 includes a singlechannel between controller 122 and non-volatile memory die 108, thesubject matter described herein is not limited to having a single memorychannel. For example, in some memory system architectures, 2, 4, 8 ormore channels may exist between the controller and the memory die,depending on controller capabilities. In any of the embodimentsdescribed herein, more than a single channel may exist between thecontroller and the memory die, even if a single channel is shown in thedrawings.

As depicted in FIG. 2, controller 122 includes a front end module 208that interfaces with a host, a back end module 210 that interfaces withthe one or more non-volatile memory die 108, and various other modulesthat perform functions which will now be described in detail.

The components of controller 122 depicted in FIG. 2 may take the form ofa packaged functional hardware unit (e.g., an electrical circuit)designed for use with other components, a portion of a program code(e.g., software or firmware) executable by a (micro) processor orprocessing circuitry that usually performs a particular function ofrelated functions, or a self-contained hardware or software componentthat interfaces with a larger system, for example.

For example, each module may include an ASIC, an FPGA, a circuit, adigital logic circuit, an analog circuit, a combination of discretecircuits, gates, or any other type of hardware or combination thereof.Alternatively or in addition, each module may include software stored ina processor readable device (e.g., memory) to program a processor forcontroller 122 to perform the functions described herein. Thearchitecture depicted in FIG. 2 is one example implementation that may(or may not) use the components of controller 122 depicted in FIG. 1(i.e., RAM, ROM, processor, interface).

Referring again to modules of controller 122, a buffer management/buscontrol 214 manages buffers in random access memory (RAM) 216 andcontrols the internal bus arbitration of controller 122. A read onlymemory (ROM) 218 stores system boot code. Although illustrated in FIG. 2as located separately from controller 122, in other embodiments one orboth of the RAM 216 and ROM 218 may be located within controller 122. Inyet other embodiments, portions of RAM and ROM may be located bothwithin controller 122 and outside controller 122. Further, in someimplementations, controller 122, RAM 216, and ROM 218 may be located onseparate semiconductor die.

Front end module 208 includes a host interface 220 and a physical layerinterface (PHY) 222 that provide the electrical interface with the hostor next level storage controller. The choice of the type of hostinterface 220 can depend on the type of memory being used. Examples ofhost interfaces 220 include, but are not limited to, SATA, SATA Express,SAS, Fibre Channel, USB, PCIe, and NVMe. Host interface 220 typicallyfacilitates transfer for data, control signals, and timing signals.

Back end module 210 includes an error correction code (ECC) engine 224that encodes the data bytes received from the host, and decodes anderror corrects the data bytes read from the non-volatile memory. Acommand sequencer 226 generates command sequences, such as program anderase command sequences, to be transmitted to non-volatile memory die108. A RAID (Redundant Array of Independent Dies) module 228 managesgeneration of RAID parity and recovery of failed data. The RAID paritymay be used as an additional level of integrity protection for the databeing written into the non-volatile memory system 100. In some cases,the RAID module 228 may be a part of the ECC engine 224. Note that theRAID parity may be added as one more extra die as implied by the commonname, but RAID parity also may be added within the existing die, e.g.,as an extra plane, or extra block, or extra WLs within a block.

A memory interface 230 provides the command sequences to non-volatilememory die 108 and receives status information from non-volatile memorydie 108. In one embodiment, memory interface 230 may be a double datarate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface.A flash control layer 232 controls the overall operation of back endmodule 210.

Additional components of system 100 illustrated in FIG. 2 include mediamanagement layer 238, which performs wear leveling of memory cells ofnon-volatile memory die 108. System 100 also includes other discretecomponents 240, such as external electrical interfaces, external RAM,resistors, capacitors, or other components that may interface withcontroller 122. In alternative embodiments, one or more of physicallayer interface 222, RAID module 228, media management layer 238 andbuffer management/bus controller 214 are optional components that arenot necessary in controller 122.

The Flash Translation Layer (FTL) or Media Management Layer (MML) 238may be integrated as part of the flash management that may handle flasherrors and interfacing with the host. In particular, MML may be a modulein flash management and may be responsible for the internals of NANDmanagement. In particular, MML 238 may include an algorithm in thememory device firmware which translates writes from the host into writesto memory structure 126 of die 108. MML 238 may be needed because memorystructure 126: 1) may have limited endurance; 2) may only be written inmultiples of pages; and/or 3) may not be written unless it is erased asa block.

MML 238 understands these potential limitations of memory structure 126which may not be visible to the host. Accordingly, MML 238 attempts totranslate writes from host into writes into memory structure 126. Asdescribed below, erratic bits may be identified and recorded using MML238. This recording of erratic bits can be used for evaluating thehealth of blocks and/or word lines (the memory cells on the word lines).

Controller 122 may interface with one or more memory die 108. In oneembodiment, controller 122 and multiple memory die (together comprisingnon-volatile storage system 100) implement an SSD, which can emulate,replace or be used instead of a hard disk drive inside a host, as a NASdevice, in a laptop, in a tablet, in a server, etc. Additionally, theSSD need not be made to work as a hard drive.

Some embodiments of a non-volatile storage system will include onememory die 108 connected to one controller 122. However, otherembodiments may include multiple memory die 108 in communication withone or more controllers 122. In one example, the multiple memory die canbe grouped into a set of memory packages. Each memory package includesone or more memory die in communication with controller 122. In oneembodiment, a memory package includes a printed circuit board (orsimilar structure) with one or more memory die mounted thereon. In someembodiments, a memory package can include molding material to encase thememory dies of the memory package. In some embodiments, controller 122is physically separate from any of the memory packages.

FIG. 3 is a diagram that shows further details of one embodiment ofcircuits for applying voltages to a memory structure 126. Two blocks300, 320 of memory cells are depicted. Circuits of FIG. 3 apply voltagesto word lines and select lines. Microcontroller 112 provides controlsignals to the circuits, in one embodiment. For example, microcontroller112 may issue control signals to one or more of CONTROL 380, HighVoltage Generator (HV GEN) 372, Page Buffer Driver (PB DRV) 374, CommandRegister (CMD REG) 376 and Input/Output (I/O) Buffer 378. In anembodiment, microcontroller 112 issues control signals to CONTROL 380,which in turn controls other elements such as HV GEN 372 and PB DRV 374.

In an embodiment, HV GEN 372 is connected to word line driver 350, tocontrol magnitudes and timing of voltages. PB DRV 374 is connected topage buffer 340 to control the page buffer 340. The page buffer 340 mayinclude sense blocks, such as SB1 of FIG. 1B.

Each block of storage elements is associated with a set of transfertransistors, in one possible embodiment. For example, block 300, whichis a selected block in this example, e.g., a block in which aprogramming or sense operation is to take place, includes a drain-sideselect gate (SGD) connected to a transfer transistor 304, a drain-sidedummy word line (WLDD) connected to a transfer transistor 306, a wordline (WL47) connected to a transfer transistor 308, intermediate wordlines WL30-WL1 (not shown) connected to respective transfer transistors(not shown), a word line (WL0) connected to a transfer transistor 310, asource-side dummy word line (WLDS) connected to a transfer transistor312, and a source-side select gate (SGS) connected to a transfertransistor 314.

The control gate of each transfer transistor of block 300 is connectedto a block decoder (BD) 302 via a common path 303. The BD 302 receives avoltage from a transfer transistor driver (TT DRV) 364 and a controlsignal from an address register (ADD REG) 370. The control signalincludes an address. If the address matches an address of the BD 302, BD302 acts as a conductive switch which passes the voltage to the controlgates of the associated transfer transistors via path 303. If theaddress does not match the address of BD 302, BD 302 acts as anon-conductive switch which does not pass the voltage to the controlgates of the associated transfer transistors.

Each transfer transistor may be an n-channel MOSFET, for example, whichhas a drain node on the left hand side and a source node on the righthand side. The drain node for each transfer transistor is connected to arespective voltage driver in a set of high-voltage voltage drivers 350.Each driver may include an on-chip charge pump.

For example, the transfer transistor 304 is connected to a drain selectgate driver (SGD DRV) 352, the transfer transistor 306 is connected to adummy word line driver (WLDD DRV) 354, the transfer transistor 308 isconnected to the word line driver (WL47 DRV) 356, . . . , the transfertransistor 310 is connected to the word line driver (WL0 DRV) 358, thetransfer transistor 312 is connected to the source side dummy word linedriver (WLDS DRV) 360, and the transfer transistor 314 is connected tothe source select gate driver (SGS DRV). Each voltage driver can beindependently controlled to provide a desired output voltage.

A similar arrangement is used for the example unselected block 320,which includes a transfer transistor 324 connected to SGD and SGD DRV352, a transfer transistor 326 connected to WLDD and WLDD DRV 354, atransfer transistor 328 connected to WL47 and WL47 DRV 356, . . . , atransfer transistor 330 connected to WL0 and WL0 DRV 358, a transfertransistor 332 connected to WLDS and WLDS DRV 360, and a transfertransistor 334 connected to SGS and SGS DRV 362.

The control gates of the transfer transistors of unselected block 320are connected to a respective block decoder (BD) 322 via a common path323. BD 322 also is connected to TT DRV 364 to receive a voltage, and toaddress register 370 to receive a control signal which instructs BD 322to pass or not pass the voltage to the control gates of the associatedtransfer transistors via path 323. Address register (ADD REG) 370 alsocommunicates with the voltage drivers in the set of high-voltage voltagedrivers 350.

A number of bit lines (BLs) 342 extend across the selected block 300 andthe unselected block 320 (and across additional unselected blocks, notshown, in some implementations) and into a page buffer 340, which isresponsive to column decoder 132. Page buffer 340 stores data which arewritten into, or read from, a selected word line of the selected block.

During an operation of the memory device, address register 370 providesa data load command to an input-output buffer 378 and to a commandregister 376. Input-output buffer 378 provides the command to pagebuffer 340. Command register 376 provides a command to a control circuit380, which instructs a high voltage generator 372 to control voltagedrivers 350 at appropriate levels.

Typically, during programming, the driver of the selected word lineprovides a programming level voltage, such as 12-26 V and the unselectedword lines receive a pass voltage V_(PASS) such as 4-6 V. Duringsensing, the driver of the selected word line provides a read or verifylevel voltage (V_(CGR) or V_(VERIFY), respectively), while theunselected word lines receive a read pass voltage, V_(READ-PASS).Control 380 also instructs the page buffer driver (PB DRV) 374 tocontrol page buffer 340. Address register 370 also communicates withcolumn decoder 132.

The memory systems discussed above can be erased, programmed/written andread. At the end of a successful programming process (withverification), the threshold voltages of the memory cells should bewithin one or more distributions of threshold voltages for programmedmemory cells or within a distribution of threshold voltages for erasedmemory cells, as appropriate. FIG. 4 illustrates example thresholdvoltage distributions for the memory cell array when each memory cellstores three bits of data. Other embodiments, however, may use otherdata capacities per memory cell (e.g., such as one, two, four, or fivebits of data per memory cell).

FIG. 4 shows eight threshold voltage distributions, corresponding toeight data states. The first threshold voltage distribution (data state)S0 represents memory cells that are erased. The other seven thresholdvoltage distributions (data states) S1-S7 represent memory cells thatare programmed and, therefore, also are called programmed states. Eachthreshold voltage distribution (data state) corresponds to predeterminedvalues for the set of data bits.

The specific relationship between the data programmed into the memorycell and the threshold voltage levels of the cell depends upon the dataencoding scheme adopted for the cells. In one embodiment, data valuesare assigned to the threshold voltage ranges using a Gray codeassignment so that if the threshold voltage of a memory erroneouslyshifts to its neighboring data state, only one bit will be affected.

FIG. 4 also shows seven read reference voltages, Vr1, Vr2, Vr3, Vr4,Vr5, Vr6, and Vr7, for reading data from memory cells. By testing (e.g.,performing sense operations) whether the threshold voltage of a givenmemory cell is above or below the seven read reference voltages, thesystem can determine what data state (e.g., S0, S1, S2, S3, . . . ) amemory cell is in.

FIG. 4 also shows seven verify reference voltages, Vv1, Vv2, Vv3, Vv4,Vv5, Vv6, and Vv7. When programming memory cells to data state S1, thesystem will test whether those memory cells have a threshold voltagegreater than or equal to Vv1. When programming memory cells to datastate S2, the system will test whether the memory cells have thresholdvoltages greater than or equal to Vv2. When programming memory cells todata state S3, the system will determine whether memory cells have theirthreshold voltage greater than or equal to Vv3. When programming memorycells to data state S4, the system will test whether those memory cellshave a threshold voltage greater than or equal to Vv4. When programmingmemory cells to data state S5, the system will test whether those memorycells have a threshold voltage greater than or equal to Vv5. Whenprogramming memory cells to data state S6, the system will test whetherthose memory cells have a threshold voltage greater than or equal toVv6. When programming memory cells to data state S7, the system willtest whether those memory cells have a threshold voltage greater than orequal to Vv7.

In one embodiment, known as full sequence programming, memory cells canbe programmed from the erased data state S0 directly to any of theprogrammed data states S1-S7. For example, a population of memory cellsto be programmed may first be erased so that all memory cells in thepopulation are in erased data state S0. Then, a programming process isused to program memory cells directly into data states S1, S2, S3, S4,S5, S6, and/or S7.

For example, while some memory cells are being programmed from datastate S0 to data state S1, other memory cells are being programmed fromdata state S0 to data state S2 and/or from data state S0 to data stateS3, and so on. The arrows of FIG. 4 represent the full sequenceprogramming. The technology described herein can also be used with othertypes of programming in addition to full sequence programming(including, but not limited to, multiple stage/phase programming). Insome embodiments, data states S1-S7 can overlap, with controller 122relying on ECC to identify the correct data being stored.

In one embodiment, when a block is subjected to an erase operation, allmemory cells are moved to data state S0, the erased state. The proposedtechnology described herein can be used for embodiments in which eachmemory cell stores one bit of data per memory cell (also referred to asSLC) and for embodiments in which each memory cell stores multiple bitsof data per memory cell (FIG. 4). When memory cells store one bit ofdata per memory cell, there may be two data states. When memory cellsstore two bits of data per memory cell, there may be four data states.

FIG. 5 is a flowchart describing one embodiment of a process forprogramming. In one example embodiment, the process of FIG. 5 isperformed on memory die 108 using the one or more control circuitsdiscussed above (see FIG. 1), at the direction of microcontroller 112.The process of FIG. 5 also can be used to implement the full sequenceprogramming discussed above. The process of FIG. 5 also can be used toimplement each phase of a multi-phase programming process. Additionally,the process of FIG. 5 can be used to program memory cells connected tothe same word line with one bit of data per memory cell.

Typically, the program voltage applied to the control gates (via aselected word line) during a program operation is applied as a series ofprogram pulses. Between programming pulses are a set of verify pulses toperform verification. In many implementations, the magnitude of theprogram pulses is increased with each successive pulse by apredetermined step size. In step 570 of FIG. 5, the programming voltage(Vpgm) is initialized to the starting magnitude (e.g., 12-16V or anothersuitable level) and a program counter PC maintained by microcontroller112 is initialized at 1.

In step 572, a program pulse of the program signal Vpgm is applied tothe selected word line (the word line selected for programming). In oneembodiment, the group of memory cells being programmed concurrently areall connected to the same word line (the selected word line). Theunselected word lines receive one or more boosting voltages (e.g., ˜7-11volts) to perform boosting schemes known in the art. If a memory cellshould be programmed, then the corresponding bit line is grounded. Onthe other hand, if the memory cell should remain at its currentthreshold voltage, then the corresponding bit line is connected to Vddto inhibit programming.

In step 572, the program pulse is concurrently applied to all memorycells connected to the selected word line so that all of the memorycells connected to the selected word line are programmed concurrently.That is, they are programmed at the same time or during overlappingtimes (both of which are considered concurrent). In this manner all ofthe memory cells connected to the selected word line will concurrentlyhave their threshold voltage change, unless they have been locked outfrom programming.

In step 574, the appropriate memory cells are verified using theappropriate set of verify reference voltages to perform one or moreverify operations. In one embodiment, the verification process isperformed by applying the testing whether the threshold voltages of thememory cells selected for programming have reached the appropriateverify reference voltage.

In step 576, it is determined whether all the memory cells have reachedtheir target threshold voltages (pass). If so, the programming processis complete and successful because all selected memory cells wereprogrammed and verified to their target data states. A status of “PASS”is reported in step 578. If, in 576, it is determined that not all ofthe memory cells have reached their target threshold voltages (fail),then the programming process continues to step 580.

In step 580, the system counts the number of memory cells that have notyet reached their respective target threshold voltage distribution. Thatis, the system counts the number of memory cells that have, so far,failed the verify process. This counting can be done by microcontroller112, controller 122, or other logic. In one implementation, each of thesense blocks will store the status (pass/fail) of their respectivecells. In one embodiment, there is one total count, which reflects thetotal number of memory cells currently being programmed that have failedthe last verify step. In another embodiment, separate counts are keptfor each data state.

In step 582, it is determined whether the count from step 580 is lessthan or equal to a predetermined limit. In one embodiment, thepredetermined limit is the number of bits that can be corrected by errorcorrection codes (ECC) during a read process for the page of memorycells. If the number of failed memory cells is less than or equal to thepredetermined limit, than the programming process can stop and a statusof “PASS” is reported in step 578. In this situation, enough memorycells programmed correctly such that the few remaining memory cells thathave not been completely programmed can be corrected using ECC duringthe read process. In some embodiments, step 580 will count the number offailed cells for each sector, each target data state or other unit, andthose counts will individually or collectively be compared to athreshold in step 582.

In another embodiment, the predetermined limit can be less than thenumber of bits that can be corrected by ECC during a read process toallow for future errors. When programming less than all of the memorycells for a page, or comparing a count for only one data state (or lessthan all states), than the predetermined limit can be a portion(pro-rata or not pro-rata) of the number of bits that can be correctedby ECC during a read process for the page of memory cells. In someembodiments, the limit is not predetermined. Instead, it changes basedon the number of errors already counted for the page, the number ofprogram-erase cycles performed or other criteria.

If number of failed memory cells is not less than the predeterminedlimit, than the programming process continues at step 584 and theprogram counter PC is checked against the program limit value (PL).Examples of program limit values include 12, 20 and 30; however, othervalues can be used. If the program counter PC is not less than theprogram limit value PL, then the program process is considered to havefailed and a status of FAIL is reported in step 588. This is one exampleof a program fault.

If the program counter PC is less than the program limit value PL, thenthe process continues at step 586 during which time the Program CounterPC is incremented by 1 and the program voltage Vpgm is stepped up to thenext magnitude. For example, the next pulse will have a magnitudegreater than the previous pulse by a step size (e.g., a step size of0.1-0.5 volts). After step 586, the process loops back to step 572 andanother program pulse is applied to the selected word line so thatanother iteration (steps 572-586) of the programming process of FIG. 5is performed.

In general, during verify operations and read operations, the selectedword line is connected to a voltage (one example of a reference signal),a level of which is specified for each read operation (e.g., see readreference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, of FIG. 4) orverify operation (e.g., see verify reference voltages Vv1, Vv2, Vv3,Vv4, Vv5, Vv6, and Vv7 of FIG. 4) to determine whether a thresholdvoltage of the concerned memory cell has reached such level. Afterapplying the word line voltage, the conduction current of the memorycell is measured to determine whether the memory cell turned on(conducted current) in response to the voltage applied to the word line.

If the conduction current is measured to be greater than a certainvalue, then it is assumed that the memory cell turned ON and the voltageapplied to the word line is greater than the threshold voltage of thememory cell. If the conduction current is not measured to be greaterthan the certain value, then it is assumed that the memory cell did notturn ON and the voltage applied to the word line is not greater than thethreshold voltage of the memory cell. During a read or verify process,the unselected memory cells are provided with one or more read passvoltages at their control gates so that these memory cells will operateas pass gates (e.g., conducting current regardless of whether they areprogrammed or erased).

There are many ways to measure the conduction current of a memory cellduring a read or verify operation. In one example, the conductioncurrent of a memory cell is measured by the rate it discharges orcharges a dedicated capacitor in the sense amplifier. In anotherexample, the conduction current of the selected memory cell allows (orfails to allow) the NAND string that includes the memory cell todischarge a corresponding bit line. The voltage on the bit line ismeasured after a period of time to see whether it has been discharged ornot. Note that the technology described herein can be used withdifferent methods known in the art for verifying/reading. Other read andverify techniques known in the art can also be used.

In some embodiments, controller 122 receives a request from the host (ora client, user, etc.) to program host data (data received from the host)into the memory system. In some embodiments, controller 122 arranges thehost data to be programmed into units of data. For example, controller122 can arrange the host data into pages, partial pages (a subset of apage), word line units, blocks, jumbo blocks, or other units.

Step 572 of FIG. 5 includes applying a program voltage pulse on theselected word line. Step 574 of FIG. 5 includes verification, which insome embodiments comprises applying the verify reference voltages on theselected word line. As steps 572 and 574 are part of an iterative loop,the program voltage is applied as a series of voltage pulses that stepup in magnitude. Between voltage pulses, verify reference voltages areapplied.

FIG. 6 is a flowchart of one embodiment of applying a program pulse andprogramming voltages that may be used in step 572 of FIG. 5. Thisprocess is used to program 3D NAND in one embodiment. FIG. 6 showstiming of various signals during one embodiment of the process of FIG.6. The MCU 112 controls the timing and magnitudes of the signals in FIG.6, in one embodiment. Note that the various signals in FIG. 6 are justone example of voltages applied to the memory structure 126 during amemory operation. The timing of the signals in FIG. 6 is controlled byCTC signals, in an embodiment.

A low voltage is applied to the source line at step 622. Referring toFIG. 6, the common source line SL is raised to a low voltage Vsrc (e.g.,about 1.0V-1.5V) at time t0 where it remains for the duration of theprogramming process. The source line SL is kept at 0V in someembodiments. The source select line SGS remains at 0V to place thesource select transistors into isolation mode. As one example this couldbe on the order of 1.0V-1.5V. Note that the other signals in FIG. 6 areat 0V at time t0.

At step 624, the data is applied to the bit lines. The data may beapplied to the bit lines based on whether a memory cell in the NANDstrings that are in the present programming operation is to beprogrammed. If the memory cell is to be programmed, then its associatedbit line has a program enable voltage (e.g., Vbl_Program_Enable) appliedto it. If the memory cell is not to be programmed, then its associatedbit line has a program inhibit voltage (e.g., Vbl_Inhibit) applied toit.

Referring to FIG. 7, line 752 shows the bit line voltage at 0V for aNAND string (in the set that are a part of the present programmingoperation) having a memory cell at the selected word line WLn that is tobe programmed. Line 750 shows the bit line voltage at V_(DD) for a NANDstring (in the set that are a part of the present programming operation)having a cell at WLn that is to be inhibited from programming. V_(DD)designates program inhibit and is often referred to as a program inhibitvoltage. Note that line 752 represents one example of V_Program_Enable,and that line 750 represents one example of Vbl_Inhibit.

Step 626 is to apply Vsgds to selected drain side select lines. Step 628is to apply Vsgdu to unselected drain side select lines. Note that FIG.7 shows two SGD lines. Line SGDs refers to a drain side select linehaving at least one NAND string that is currently programming. Line SGDurefers to a drain side select line having no NAND strings currentlyprogramming.

Referring to FIG. 7, at time t₃, drain side select line SGDs is raisedto Vsgds, and drain side select line SGDu is raised to Vsgdu. Thevoltage Vsgds turns on the drain side select transistor for NAND stringshaving a memory cell being programmed. Note that Vbl_Program_Enable isbeing applied to the selected bit line BL0 at time t₃.

Note that at this time Vsgds may also be applied to control gates ofdrain side select transistors of NAND strings for which no memory cellshould be programmed. However, note that Vbl_Inhibit is being applied tothe unselected bit line BL1 at time t₃.

Referring again to FIG. 7, at time t3, drain side select line SGDu isset to Vsgdu. The voltage Vsgdu should keep off the associated drainside select transistor.

At step 636, a boosting voltage (e.g., V_(PASS)) is applied tounselected word lines. Note that the magnitude for V_(PASS) does notneed to be the same for each of the unselected word lines. There are avariety of boosting schemes that can be used. Examples of boostingschemes include, but are not limited to, self-boosting (SB), localself-boosting (LSB) and erase area self-boosting (EASB).

Referring to FIG. 7, at time t₄, the boosting/programming phase begins.The boosting voltages are applied to the various word lines at time t₄.In one embodiment, each unselected word line receives a boosting voltageV_(PASS). In one embodiment, the voltage applied to the unselected wordlines depends on their position relative to the selected word line.

In one embodiment, a pass voltage is applied to at least a subset ofunselected word lines during a program operation. The pass voltage istypically less than the program voltage. As one example, the passvoltage may be 8 volts. However, the pass voltage could be higher orlower. The pass voltage may assist in boosting channels of memory cells.In one embodiment, capacitive coupling between the control gate andchannel lifts the channel potential. Thus, the pass voltage that isapplied to the control gate may serve to boost the channel potential.

The program voltage VPGM is then applied to the selected word line atstep 638. With the boosting voltages applied and the inhibited NANDstring channels boosted, program disturb of unselected memory cells onthe selected word line is prevented or reduced.

Referring to FIG. 7, at time t₅, the program voltage VPGM is applied tothe selected word line WLn. Because the inhibited NAND string channel isboosted when the program voltage is applied, the unselected memory cellsat WLn for the inhibited NAND strings will not be programmed. Theboosted channel region voltage decreases the potential across thosememory cells' tunnel dielectric regions, thus preventing any inadvertentprogramming.

At step 640, the word lines, bit lines, source lines, and drain selectlines are lowered to 0V, marking the completion of one programmingiteration. It should be noted that the steps of FIG. 6 can be appliedwith each iteration of the process of FIG. 5, with the program voltagebeing increased each iteration. However, it is not required that theprogram voltage increase in magnitude with each iteration.

Referring to FIG. 7, at time t6, the word lines are lowered to 0V. Thesource and bit lines are then lowered to 0V at time t7. The drain selectline SGD is lowered to 0V at time t8.

Numerous variations to the signals depicted in FIG. 7 can be made inaccordance with embodiments. Also note that timing and/or magnitudes ofthe voltages in FIG. 7 (as well as other memory array signals) can bemodified by modifying instructions executed by the MCU 112. For example,if it is determined that the length of time for which the programmingvoltage is applied should be changed, then the instructions can bemodified to change the length of time between t5 and t6 in FIG. 7. Inone embodiment, this change is made by changing the timing ofsetting/resetting CTC signals, which in turn control the timing of thevoltages in FIG. 7. Many other modifications to memory array voltagescan be made by modifying instructions executed by the MCU 112 and/or bymodifying data that the MCU 112 uses to execute the instructions.

FIG. 8 is a high-level block diagram of one embodiment ofmicrocontroller 112, and other elements. The other elements include amemory structure 126, which contains non-volatile memory cells, firstcircuit 820, and second circuit 822. Microcontroller 112 provides on-diecontrol for reading, programming, and erasing the non-volatile memorycells of memory structure 126. Additionally, microcontroller 112provides on-die control for interfacing with controller 122.

The first circuit 820 includes a voltage generator 824 and row decoder124. The first circuit 820 is configured to apply voltages to the memorystructure 126. This may include voltages to one or more of word lines,select lines (e.g., SGD, SGS), source lines, as well as other elementsin the memory structure 126. The first circuit 820 may include decoders(e.g., row decoder 124) and charge pumps, which provide the voltages forword lines, select lines (e.g., SGD, SGS), source lines, as well asother elements in the memory structure 126. The first circuit 820 mayinclude power control circuit 116 and/or on-chip address decoder 114. Inone embodiment, the first circuit 820 includes one or more of theelements in FIG. 4 that are connected to the blocks 300, 320. Forexample, the voltage generator 824 may include high-voltage voltagedrivers 350 (each driver may include an on-chip charge pump). The rowdecoder 124 may include one or more of block decoder (BD) 322, transfertransistors 304-314, 324-334. The first circuit 820 may include otherelements from FIG. 3 such as CONTROL 380, HV GEN 372, CMD REG 376,and/or ADD REG 370. Note that the first circuit 820 is not limited tothe embodiment depicted in FIG. 3.

The second circuit 822 is configured to test conditions of thenon-volatile memory cells in response to the voltages applied to thememory structure 126. The second circuit 822 includes sensing circuit826 and column decoders 132. The sensing circuit 826 may include andcontrol sense amplifiers that sense a current of a memory cell.

In one embodiment, the sensing circuit 826 includes all or a portion ofa sense block (see, for example, SB1 in FIG. 1B). For example, sensingcircuit 826 may include sense modules (e.g., SM0, SM1, SM2, SM3) anddata latches (e.g., latches 194). In one embodiment, sensing circuit 826includes data latch processor 192 (see FIG. 1B). In one embodiment, datalatch processor 192 tests conditions of the non-volatile memory cells inresponse to the voltages applied to the memory structure 126. The secondcircuit 822 may include one or more managing circuits (e.g., MC0, FIG.1B). It is not required that the sensing circuit 826 include all of theelements in the MC0 depicted in FIG. 1B. Also, the sensing circuit 826may include elements not depicted in MC0 of FIG. 1B. In one embodiment,the second circuit 822 includes page buffer 340, PB DRV 374, and I/O 378(see, FIG. 3). Note that CONTROL 380 may be shared between the firstcircuit 820 and the second circuit 822.

The microcontroller 112 includes a core processor 802 a sense processor804, and a sequence processor 806. The sequence processor 806 may alsobe referred to as a main processor. The core processor 802 sends controlsignals to the first circuit 820. The control signals may be referred toas CTC signals. The control signals could be analog or digital signals.The control signals may be sent over a communication medium. Acommunication medium may comprise one or more signal lines. A signalline is capable of transmitting an electrical signal, such as a voltagelevel, in some embodiments. For example, a signal line may be anelectrically conductive path. A signal line is capable of transmittingan electromagnetic signal, such as an optical signal (e.g., lightpulse), in some embodiments. For example, a signal line may comprise anoptical waveguide. In embodiments, a signal line may include, but is notlimited to, one or more of a wire, trace, transmission line, track, pad,layer, lead, metal, portion of a printed circuit board or assembly,conducting material and other material that may transfer or carry anelectrical signal, and/or electromagnetic signal. In embodiments, asignal line may form one or more geometric shapes, such as a line ormultiple connected lines. In embodiments, a signal line may beunidirectional or bidirectional in transferring signals between circuitsand within circuits. Note that the communication medium may compriseelements other than the signal lines, such as drivers, buffers, or logicgates.

The core processor 802 is configured to control the first circuit 820 tocontrol analog voltages (e.g., word line voltages, select line voltages,etc.) applied by the first circuit 820 to the memory structure 126, inone embodiment. The core processor 802 is configured to control decodersand charge pumps in the first circuit 820, in one embodiment. The coreprocessor 802 is configured to control voltage levels applied by senseamplifiers, in one embodiment. Note that throughout this description,the phrase, “a processor is configured to control a circuit” or thelike, does not require that the processor control all functionality ofthe circuit.

Note that the timing of the sequences of voltages applied by the firstcircuit 820 in order to program, read, or erase memory cells may be verycomplex. In some embodiments, a core timing chart specifies the timingof the sequences of CTC signals that are used to control the voltagesapplied by the first circuit 820. FIG. 7 shows one example of timing ofthe sequences of voltages applied during a programing operation. Thecore processor 802 is configured to issue CTC signals for differentmemory operations, in one embodiment. Thus, the core processor 802 maybe configured to execute first instructions to coordinate sequences ofvoltages applied to the memory structure 126 by the first circuit 820 inorder to perform memory operations with respect to non-volatile memorycells in the memory structure 126. The memory operations could be, forexample, read, program, and/or erase operations. The core processor 802may also be referred to as a core machine (CM).

The sense processor 804 sends control signals to the second circuit 822.The control signals could be analog or digital signals. The controlsignals may be sent over a communication medium. As noted above, acommunication medium may comprise one or more signal lines, and may alsocomprise drivers, buffers, and/or logic gates. The sense processor 804is configured to execute second instructions to control the secondcircuit 822 to test conditions of the non-volatile memory cells inresponse to the voltages applied to the memory structure 126. The mannerin which the conditions may be tested may include, but is not limitedto, sensing, reading, detecting, measuring, probing, discovering,discriminating, checking, examining, and determining. For example, thesense processor may control the second circuit 822 to determine a datastate of the non-volatile memory cells. In one embodiment, the senseprocessor 804 sends control signals to data latch processor 192 (seeFIG. 1B).

In one embodiment, the sense processor 804 controls the sensing circuit826 to test conditions of non-volatile memory cells in memory structure126 in response to voltages applied to the memory structure 126 (such asreference voltages applied to the non-volatile memory cells) by thevoltage generator 824. The condition of a non-volatile memory cell canbe any physical parameter of a non-volatile memory cell. In oneembodiment, the sense processor 804 controls the sensing circuit 826 todetermine a data state (e.g., S0-S7 in FIG. 4) of memory cells. In oneembodiment, the sense processor 804 controls the sensing circuit 826 todetermine whether a memory cell conducts a current in response tovoltages applied to the memory cell by the voltage generator 824. In oneembodiment, the sense processor 804 controls the sensing circuit 826 todetermine whether the threshold voltage of a memory cell is above orbelow a reference voltage (e.g., Vr1-Vr7; Vv1-Vv7 in FIG. 4) applied tothe memory cell.

For example, with reference to FIG. 4, the sense processor 804 maycontrol the second circuit 822 to determine which of the data states(e.g., S0-S7) each of a set of memory cells is in. In one embodiment,the sense processor 804 controls the second circuit 822 to test whetherselected memory cells have a threshold voltage above or below areference voltage applied by the power control circuit 116. Thereference voltage might be one of Vr1-Vr7, with reference to FIG. 4, inthe event that a read operation is being performed. The referencevoltage might be one of Vv1-Vv7, with reference to FIG. 4, in the eventthat a program verify operation is being performed. The sense processormay alternatively be referred to as a Y processor (YP) or Y machine (YM)due to the association between sensing and the Y-decoder 132, in someembodiments. In one embodiment, the sense processor 804 executesinstructions in the second processor storage 814 in response to atrigger signal from the core processor 802. This allows the coreprocessor 802 to control the timing of sensing operations relative tothe timing of voltages applied to the memory structure 126 by the firstcircuit 820. Stated another way, this allows the activities (e.g.,sensing) of the second circuit 822 to be coordinated with the activities(e.g., applying voltages to the memory structure 126) of the firstcircuit 820. For example, during a sensing operation, the core processor802 can control the first circuit 820 to establish appropriate voltagelevels applied to memory cells; then, after appropriate voltage levelsare applied to memory cells, the core processor 802 can trigger thesense processor 804 to initiate a sensing operation (by the senseprocessor 804 controlling the second circuit 822). The trigger signalmay be an analog or digital signal. In one embodiment, the triggersignal has two states: logical high (which triggers the sense processor)and logical low (which does not trigger the sense processor).

The core processor storage 812, the sense processor storage 814, and thesequence processor storage 816 are tangible, non-transitory storage. Thenon-transitory storage could be volatile or non-volatile. The coreprocessor storage 812 is used to store first instructions that areexecuted by the core processor 802. The core processor storage 812 mayalso be used to store parameters that the core processor 802 applieswhen executing the first instructions. The sense processor storage 814is used to store second instructions that are executed by the senseprocessor 804. The sense processor storage 814 may also be used to storeparameters that the sense processor 804 applies when executing thesecond instructions. The sequence processor storage 816 is used to storethird instructions that are executed by the sequence processor 806. Thesequence processor storage 816 may also be used to store parameters thatthe sequence processor 806 applies when executing the thirdinstructions. The MCU 112 may have other processors, such as a parameterprocessor that control various memory operation parameters.

In one embodiment, a copy of the first instructions (and possiblyparameters used by core processor 802), a copy of the secondinstructions (and possibly parameters used by sense processor 804), anda copy of the third instructions (and possibly parameters used bysequence processor 806) are stored in non-volatile storage in order topersist the instructions (and possibly parameters) across power cycles.Those copies may be loaded into a volatile storage, which is accessed bythe respective processors 802, 804, 806. For example, the instructionloader 828 may load a copy of the instructions (and possibly parameters)from the memory structure 126 into the core processor storage 812, thesense processor storage 814, and the sequence processor storage 816. Inone embodiment, the instruction loader 828 is configured to update theinstructions in any of the core processor storage 812, the senseprocessor storage 814 and/or the sequence processor storage 816. Byupdate, it is meant that different instructions are stored to storage812, 814, and/or 816 (relative to a previous time instructions werestored to storage 812, 814, and/or 816) by accessing different (orupdated) instructions from memory structure 126. Note that although thecore processor storage 812, the sense processor storage 814 and thesequence processor storage 816 are depicted as within themicrocontroller 112, the core processor storage 812, the sense processorstorage 814 and/or the sequence processor storage 816 may reside outsideof the microcontroller 112.

Note that the instructions and/or parameters in the core processorstorage 812, the instructions and/or parameters in the sense processorstorage 814 and/or the instructions and/or parameters in the sequenceprocessor storage 816 can be modified to allow the operation of the coreprocessor 802 and/or sense processor 804 and/or sequence processor 806to be modified. For example, the instructions which the core processor802 executes could be modified to change the timing of applying voltagesto the memory structure 126. In one embodiment, the instructions aremodified to change when CTC signals are set/reset in order to change thetiming of applying voltages to the memory structure 126.

The core processor 802, the sense processor 804, and the sequenceprocessor 806 are able to fetch, decode, and execute instructions fromtheir respective processor storage (812, 814, 816), in one embodiment.The core processor 802, the sense processor 804 and the sequenceprocessor 806 can be implemented as microprocessors, in one embodiment.A microcontroller 112 may comprise one or more processors that processand/or execute microcode or other computer executable code (e.g., aninstruction set) to perform tasks or operations. The core processor 802,the sense processor 804 and the sequence processor 806 may each compriseelements such as of flip flops, latches, RAM/ROM, combinational logic,etc. In one embodiment, the core processor 802, the sense processor 804and the sequence processor 806 are implemented using CMOS technology.The microcontroller 112 is positioned on the substrate underneath thememory array, in one embodiment. The microcontroller 112 resides on thesame memory die as the memory structure 126, in one embodiment. Themicrocontroller 112 resides on the same memory die as the memorystructure 126, first circuit 820, and second circuit 822, in oneembodiment.

In some embodiments, the MCU 112 pre-computes information from which CTCsignals may be derived. In one embodiment, the pre-computed informationincludes conditions that are relevant for the non-volatile memorystructure 126 and from which the control signals for a type of memoryoperation are derivable. In one embodiment, the pre-computed informationincludes set/reset information that specifies when the CTC signals areto be set or reset. The pre-computed information may be stored in coreprocessor storage 812, the sense processor storage 814, and/or thesequence processor storage 816. In one embodiment, the information ispre-computed and stored during a power on phase. However, theinformation could be pre-computed and stored after the power on phase.The MCU 112 may access the pre-computed information during runtime inorder to generate the CTC signals for the type of memory operation.Therefore, time and/or power may be saved each time that a memoryoperation of the type is executed at runtime.

The instruction loader 828 may take the form of packaged functionalhardware unit (e.g., an electrical circuit) designed for use with othercomponents, a portion of a program code (e.g., software or firmware)executable by a (micro)processor or processing circuitry (or one or moreprocessors) that usually performs a particular function of relatedfunctions, or a self-contained hardware or software component thatinterfaces with a larger system, for example. For example, eachinstruction loader 828 may include an application specific integratedcircuit (ASIC), a Field Programmable Gate Array (FPGA), a circuit, adigital logic circuit, an analog circuit, a combination of discretecircuits, gates, or any other type of hardware or combination thereof.Alternatively, or in addition, instruction loader 828 may include orcomprise software stored in a processor readable device (e.g., memory)to program a one or more processors to perform the functions describedherein.

FIG. 9 is a more detailed block diagram of one embodiment ofmicrocontroller 112. In one embodiment, the circuit of FIG. 9 is anexample implementation of the circuit of FIG. 8. Command synchronizer902, which receives commands from controller 122, is connected toSequence processor 806. FIG. 9 shows Sequence processor 806 connected toparameter manager 906, Command (CMD) FIFO 922, FIFO manager 924, andsense processor 804. Parameter FIFO 920 is connected to parametermanager 924 and FIFO manager 924. CMD FIFO is also connected to FIFOmanager 924. Core processor 802 is connected to FIFO manager 924, senseprocessor 804 and a plurality of ROM Groups (ROM Group 0, ROM Group 1, .. . ROM Group N). Core processor 802 is connected to the first circuit820. Sense processor 804 is connected to second circuit 822. Memorystructure 126 is connected to first circuit 820 and second circuit 822.In one embodiment, all of the components depicted in FIG. 9 are on thesame memory die.

Sequence processor 806 includes a processor (e.g., a ROM or RAM, and atleast one control unit that fetches data and instructions from RAM/ROMand performs some logic operation), parameter manager 906 includes aprocessor, FIFO manager 924 includes a combinational logic circuit, coreprocessor 802 includes a processor, and sense processor 804 includes aprocessor. In one embodiment, all of the components of FIG. 9 receivethe same clock signal.

Command synchronizer 902 receives commands from controller 122 andsynchronizes the command to the clock signal. It then encodes thecommands and sends the commands to sequence processor 806, where controlof the internal flow takes place.

Sequence processor 806, which is the master of parameter manager 906 andFIFO manager 924, executes each command. It works out the clock sequenceto provide main clock and sub-clock initiators downstream. For each mainclock, sequence processor 806 starts the parameter manager 906(Parameter Control Signal 934)) to perform calculations such as biasingvoltages and temperature calibration. For each sub-clock, sequenceprocessor 806 sends a command packet 930 to CMD FIFO 922. That commandpacket 930 is decoded by the slave modules FIFO manager 924, coreprocessor 802 and sense processor 804 to execute the operation.Parameter manager provides its output to Parameter FIFO 920, which canthen be accessed by FIFO manager 924. Sequence processor 806 alsoprovides a signal 932 to suspend an operation being performed.

Sequence processor 806 is connected to CTC cache 938 a. CTC cache 938 amay be used to store conditions from which the CTC signals for a type ofmemory operation, or segment thereof, may be generated. Note that is itnot required to store the conditions for all types of memory operations.In one embodiment, the conditions are computed by the sequence processor806 during a power on phase and stored in the CTC cache 938 a. In oneembodiment, the conditions are computed by the sequence processor 806during runtime and stored in the CTC cache 938 a during runtime (butbefore a request to perform a memory operation of a certain type isreceived). In one embodiment, during runtime, when a request to performa memory operation of that type is received, the sequence processor 806accesses these stored conditions rather than computing the conditions.Accessing the stored conditions may allow the sequence processor 806 tomeet a timing budget. For example, the sequence processor 806 may have alimited number of clock cycles to determine the conditions for aparticular segment of a memory operation. For some segments of somememory operations, there might not be enough clock cycles for thesequence processor 806 to compute the conditions.

Core processor 802 is a slave to FIFO manager 924. Core processor 802generates control signals (e.g., CTC signals) for first circuit 820.Thus, core processor 802 manages the voltage signals to one or more ofword lines, bit lines, select lines (e.g., SGD, SGS), source lines, aswell as other elements in the memory structure 126. In one embodiment,core processor 802 is processor 804 of FIG. 8, or performs the samefunctions and controls the same signals as processor 804. For eachsub-clock, core processor 802 takes a command packet 930 (or multiplecommand packets) from CMD FIFO 922 (via FIFO manager 924) and mayperform a look-up and use the result of the look-up to generate the CTCsignals to first circuit 820 in order to update the voltage signals tomemory structure 126. In one embodiment, the voltage signals to memorystructure 126 are divided into groups of signals where the signals of agroup are updated together. Based on the conditions at each moment, coreprocessor 802 may perform a look-up for each group to modify the signalsfor that particular group.

Core processor 802 is connected to the plurality of ROM Groups (ROMGroup 0, ROM Group 1, . . . ROM Group N). In one embodiment, each ROMGroup stores information to perform one operation (e.g., read, write,erase, etc.). In another embodiment, each ROM Group stores informationto perform one option for an operation or part of an operation. In yetanother embodiment, each ROM Group stores information to generate onewaveform for an operation.

Core processor 802 is connected to CTC cache 938 b. CTC cache 938 b maybe used to store information from which CTC signals may be generated. Inone embodiment, this information is computed during a power on phase andstored in the CTC cache 938 b. However, the information may be computedand stored in the CTC cache 938 b after the power on phase. In oneembodiment, this information includes conditions from which the CTCsignals are derivable. These conditions may be computed by the sequenceprocessor 806. In one embodiment, this information may include set/resetinformation that indicates when voltages applied to the memory structure126 are to be set or reset. Note that it is not required to use both CTCcache 938 a and CTC cache 938 b. In one embodiment, both caches 938 a,938 b are used. In one embodiment, only CTC cache 938 a is used. In oneembodiment, only CTC cache 938 b is used. The CTC caches 938 a, 938 bmay be implemented in volatile or non-volatile storage. In oneembodiment, CTC latches 938 a, 938 b are implemented by latches.

Sense processor 804 generates and applies a set of control signals tosecond circuit 822, which is configured to test conditions of thenon-volatile memory cells in response to the voltages applied to thememory structure 126. In one embodiment, sense processor 804 isprocessor 806 of FIG. 8, or performs the same functions and controls thesame signals as processor 806. The command packets 930 may also includecontrol information for sense processor 804 to perform tasks. Senseprocessor 804 provides Feedback 936 to Sequence processor 806.

FIG. 10A is a diagram that shows how a CTC signal may be used to controla voltage waveform during an embodiment of a memory operation. A CTCsignal 1002, referred to as SGD_S/R is used to control the voltagewaveform 1004 referred to as SGDs. The timing is performed in relationto what are referred to herein as “sub-clocks” 1006. A sub-clock refersto a specific segment of a memory operation. There 16 sub-clocks 1006 inthe example in FIG. 10A. The sub-clocks 1006 do not necessarily eachhave the same time duration. In this example, the CTC signal 1002 is SETduring sub-clock 4, RESET during sub-clock 9, and SET during sub-clock13. As a result, the voltage waveform 1004 transitions from a steadystate value (e.g., 0V) to a level of Vg_pg at sub-clock 4, transitionsback down to the steady state value at sub-clock 9, and transitions fromthe steady state value to Vsgds at sub-clock 13. In some embodiments,the magnitudes of Vg_pg and Vsgds are controlled by the Analog Signalsfrom the parameter manager 906.

The CTC signal 1002 is one of many CTC signals that are issued tocontrol different memory operations. In one embodiment, a specificationdescribes the pulse shapes (e.g., start times, durations, magnitudes).This specification could cover waveforms such as the examples in FIG. 7for a programming operation, as well as many other memory operations.From this specification, a combination of Excel macros and a script maybe used to generate a set/reset (SR) table, which defines on what timeand under what conditions each CTC signal needs to be set or reset. Fromthis SR table, a master table may be generated.

FIG. 10B depicts one example of a portion of a master table 1050 for CTCsignals. The column labeled “CTC signal” specifies the CTC signal forthat row of master table 1050. A total of five different CTC signals areshown in the table, but typically there are many more CTC signals. Forexample, there could be more than 100 different CTC signals. In oneembodiment, there are about 160 different CTC signals.

The mode column specifies the mode for the CTC signal for that row. Inthis example, the modes include program and read. There could be othermodes such as verify and erase. The sub-mode column specifies thesub-mode for the CTC signal for that row. For the program mode, there isan “all bit line” (ABL) program mode, an SLC program mode, and an MLCprogram mode. There may be many other sub-modes for the program mode.For the read mode, there is an SLC read mode, and an MLC read mode.There may be many other sub-modes for the read mode.

The main clock column specifies the main clock for the CTC signal inthat row. Two main clocks are shown (P_CLK for program, and R_CLK forread). It could take more than one main clock to complete a memoryoperation such as program or read. For example, the time frame for thevoltage waveforms in FIG. 7 may correspond to a P_CLK. There may beadditional main clocks needed to complete the program operation. In oneembodiment, there are about 20 different main clocks.

The sub-clock column specifies the sub-clock for the CTC signal in thatrow. A sub-clock defines a segment of a memory operation. The sub-clocksdo not necessarily last the same time. Hence, the segments may havedifferent durations. A sub-clock is a portion of main clock, in oneembodiment. For example, the time frame for the voltage waveforms inFIG. 7 may contain numerous different sub-clocks. As one example, eachtime (t0, t1, etc.) in FIG. 7 may correspond to a sub-clock. However,note that there may be additional sub-clocks to account for the need tochange a voltage waveform not depicted in FIG. 7. As a further example,the time period in FIG. 10A may correspond to one main clock, which has16 sub-clocks. Note that the sub-clocks in FIG. 10A may be given namessuch as p1, p2, etc. to distinguish over sub-clocks associated withother main clocks. In one embodiment, there are about 130 differentsub-clocks.

In one embodiment, the condition column specifies the condition underwhich the CTC signal in that row is to be set or reset during thesub-clock. The conditions are calculated based on a Boolean equation inone embodiment. The various letters (A, B, etc.) in the table 1050pertain to various factors that indicate whether the condition is metfor the sub-clock. For example, one of the factors might be whether avoltage (e.g., program voltage, boost voltage, kick voltage, readvoltage, etc.) should be initiated or stopped. Another factor could be amode of operation (e.g., SLC, MLC, ABL). There could potentially behundreds, or even thousands of different conditions.

The Set/Reset column specifies whether the CTC signal in that row is tobe set or reset during the sub-clock in response to the condition beingmet.

FIG. 11A illustrates an embodiment of a packet 1100 that containsinformation that may be used by the MCU 112 to generate one or more CTCsignals. The packet 1100 is generated by the sequence processor 806, inan embodiment. The sequence processor 806 places the packet into CMDFIFO queue 922, in an embodiment. The core processor 802 accesses thepacket 1100 from the FIFO and decodes the packet. Based on informationin the packet 1100, the core processor 802 generates CTC signals. Theremay be multiple such packets 1100 for a single memory operation, in anembodiment. For example, the core processor 802 may process multiplepackets 1100 in order to generate the CTC signals for a memory command(e.g., read command, write command, or erase command).

The packet 1100 contains a sub-clock field 1104, which contains a labelfor the sub-clock of the memory command. As noted above, a sub-clockrefers to a segment of a memory command. The label is specified as adigital value, in an embodiment. A timer field 1102 specifies the numberof clock cycles for the sub-clock.

Many sub-clocks only need a single packet. However, in some cases, morethan one packet is used for a single sub-clock. A last packet (LP) field1106 indicates whether this is the last packet in a multiple packetsequence for this sub-clock. This field 1106 may be a single bit.

A parameter machine (PM) field 1108 indicates whether the parametermanager 906 needs to refresh the parameter FIFO queue 920 output. Thus,note that a packet may be used to by the parameter manager 906, as wellas the core processor 802.

Condition bit map 1110 is a bit map that specifies the conditions thatapply for this sub-clock. The conditions are applicable to at least oneCTC signal, in an embodiment. The CTC signals are divided into groups,in an embodiment. Thus, the conditions that are met for this sub-blockare not necessarily applicable to each group of CTC signals. Each bit inthe condition bit map 1110 specifies a different condition, in anembodiment. In one embodiment, the condition bit map 1110 is 18 bits.However, the condition bit map 1110 could be larger or smaller. In somecases, there may be more conditions for a sub-clock than there are bitsin the condition bit map. In this case, more than one packet 1100 may beused to specify all of the conditions for this sub-clock. The lastpacket field is used to indicate whether or not there is another packetfor the sub-clock. Note that there may be hundreds, or even thousands ofpossible conditions. Therefore, it will be appreciated that differentconditions are being specified by the specific bits in the condition bitmap for different sub-clocks.

In one embodiment, for some types of memory operations, the sequenceprocessor 806 computes the conditions for the condition bit map 1110 inreal time, as the memory operation is being processed. However, forother types of memory operations, the sequence processor 806 does notcompute the conditions for the condition bit map 1110 in real time. Theforegoing may apply on a sub-clock basis. Thus, for one sub-clock of amemory operation, the sequence processor 806 may compute the conditionsfor the condition bit map 1110 in real time, as the memory operation isbeing processed. However, for another sub-clock of the memory operation,the sequence processor 806 does not compute the conditions for thecondition bit map 1110 in real time.

In one embodiment, the use cache (UC) flag 1114 indicates that cached(or stored) information should be used by the core processor 802 insteadof the condition bit map 1110. Thus, in one embodiment, when the UC flag1114 is set, the condition bit map 1110 is not valid. Instead, when thecore processor 802 decodes the packet 1100, the core processor 802 willuse cached information (e.g., a cached condition bit map in CTC cache938 b) instead. Thus, the sequence processor 806 need not compute thecondition bit map 1110 in real time. As an alternative, the sequenceprocessor 806 could access the cached information (e.g., a cachedcondition bit map in CTC cache 938 a) and use that to fill in thecondition bit map 1110 in the packet 1100. Again, the sequence processor806 need not compute the condition bit map 1110 in real time. However,in the event that the sequence processor 806 uses cached information inthe CTC cache 938 a, and the core processor 802 does not use cachedinformation in CTC cache 938 b, the UC flag 1114 is not set. In otherwords, since in this case the core processor 802 does not use cachedinformation in CTC cache 938 b, there is no need to set the UC flag 1114to instruct the core processor 802 to use cached information in CTCcache 938 b.

The Y OP field 1112 contains control information for the sense processor804. Thus, the packet 1100 may be used to control operation of the senseprocessor 804, in an embodiment. The Create Cache flag (CC) 1116 is setto 0 for packet 1100, which indicates that the core processor 802 is notto create a cache entry in CTC cache 938 b for packet 1100. The CreateCache flag (CC) 1116 will be discussed in more detail in connection withFIG. 11B.

In one embodiment, the sequence processor 806 sends a packet to the coreprocessor 802 during a power on phase in order to instruct the coreprocessor 802 to cache information in the packet. In one embodiment, thesequence processor 806 sends a packet to the core processor 802 duringruntime in order to instruct the core processor 802 to cache informationin the packet. FIG. 11B illustrates another embodiment of a packet 1130that contains a Create Cache flag (CC) 1116, which is set to 1 toindicate that an entry is to be created in CTC cache 938 b. Packet 1130has a CTC entry 1117, which is cached in the CTC cache 938 b. Thus, theCreate Cache flag (CC) 1116 indicates to the core processor 802 that theCTC entry 1117 should be cached in CTC 938 b for future use. The packet1130 in FIG. 11B contains a sub-clock field 1104 and a Group Index field1120. In one embodiment, the Group Index field 1120 occupies the samebits that were used in packet 1100 for the timer 1102, which is not usedin packet 1130. The Group Index 1120 may be used to specify a group ofsignals. As has been discussed in connection with FIG. 9, the CTCsignals may be divided into groups. Thus, when storing the CTC entry1117, the information may be stored with an indication that it isspecific to one group of CTC signals. Note that it is not required touse the packet in FIG. 11B to cache the information. In one embodiment,the information is directly cached by, for example, the sequenceprocessor 806. Also, there is no need for fields for LP 1106, PM 1108,YOP 1112, or UC 1114 in packet 1130. In one embodiment, the CTC entry1117 occupies the same number of bits as the LP 1106, PS 1108, conditionbit map 1110, Y OP 1112, and UC 1114 in packet 1100. For example, theCTC entry 1117 may be 30 bits. The LP 1106, PS 1108, condition bit map1110, Y OP 1112, and UC 1114 may combined be 30 bits. However, more orfewer than 30 bits could be used.

FIG. 12 depicts a flowchart of one embodiment of a process 1200 ofgenerating CTC signals for a memory operation or segment thereof.Process 1200 is performed by MCU 112. In one embodiment, steps 1202-1206may be performed during a power on phase. Steps 1208-1214 may beperformed during an operational phase in which requests to perform thememory operation are received. Note the process 1200 is not required tobe performed for all types of memory operations. For example, process1200 might be performed for a read operation, but not be performed foran erase operation or a program operation. Also, even if process 1200 isperformed for a memory operation (e.g., an MLC read), the process 1200is not required to be performed for all sub-clocks of the memoryoperation.

Step 1202 includes accessing parameters from storage on the non-volatilememory system. In one embodiment, MCU 112 accesses the parameters frombuffers 130. The parameters may include default parameters, voltages,and the like for memory operations.

Step 1204 includes computing information for generating CTC signals forat least one segment of a memory command, based on the parameters. Inone embodiment, separate information is computed for each segment forwhich information is pre-computed. In one embodiment, the informationincludes the condition bit map 1110. In one embodiment, the informationincludes the CTC entry 1117. In one embodiment, the MCU 112 computes thecondition bit map 1110 (or alternatively the CTC entry 1117) for asub-clock of a memory operation or segment of the memory operation. Inone embodiment, the condition bit map 1110 (or alternatively the CTCentry 1117) is computed based on a combination of modes (or sub-modes),parameters, and/or state dependent bits. In one embodiment, theinformation includes set/reset information that indicates whether avoltage applied to the memory structure 126 is to be set or reset duringa sub-clock of the memory operation. In one embodiment, the MCU 112computes the set/reset information.

Step 1206 includes storing the information that was computed in step1204. In one embodiment, the information is stored in latches in the MCU112. In one embodiment, the information is stored in CTC cache 938 a.For example, sequence processor 806 may store the information in CTCcache 938 a. In some embodiments, the information is stored in CTC cache938 b.

In one embodiment of step 1206, the sequence processor 806 places apacket (e.g., packet 1130 in FIG. 11B) on the CMD FIFO 922, which isaccessed by the core processor 802. The packet may contain a CTC entry1117, which was computed by the sequence processor 806 in step 1204. Thepacket may also contain a CC flag 1116, which is set to 1 to indicatethat the condition bit map 1110 should be cached in CTC 938 b by thecore processor 802. The core processor 802 decodes the packet and maystore the information in the CTC cache 938 b.

However, it is not required to use this technique in which the sequenceprocessor 806 sends the packet 1130 to be able to cache the information.In one embodiment of step 1206, the sequence processor 806 stores theinformation in CTC cache 938 b, without generating a packet 1130. Forexample, the sequence processor 806 may compute conditions that wouldotherwise be placed in the condition bit map. The sequence processor 806may store the computed conditions directly into the CTC cache 938 b.

Steps 1208-1214 are performed during an operational phase. Steps1208-1214 may be repeated each time a request to perform the memoryoperation is received. Step 1208 includes receiving a request to performthe memory operation. In one embodiment, command synchronizer 902receives the request from controller 122, and provides the request tosequence processor 806.

Step 1210 includes accessing the stored information for the at least onesegment. In some embodiments, the information is stored on a sub-clockbasis. It is not required that step 1210 be performed for all sub-clocksof the memory operation. In one embodiment, the core processor 802accesses the information from the CTC cache 938 b. In one embodiment,the sequence processor 806 accesses the information from CTC cache 938a.

Step 1212 includes setting or resetting one or more CTC signals for theat least one segment based on the stored information that was accessedin step 1210. As noted above, in one embodiment step 1210 is performedfor at least one sub-clock of the memory operation. Hence, step 1212 isnot required to be performed for all sub-clocks of the memory operation.In the event that steps 1210 and 1212 are not performed for a sub-clock,setting or resetting of the CTC signals (for other sub-clocks) may beperformed based on computations performed at runtime.

Step 1214 includes using the CTC signals to control the at least onesegment of the memory operation. Step 1214 may also include using CTCsignals that were computed at runtime to control other segments of thememory operation.

Process 1200 may be modified such that steps 1202-1206 are performedduring the operational phase. In this case, steps 1202-1206 may still beperformed prior to receiving at least some of the memory accesscommands. Therefore, benefits described herein of time and/or powersavings may be realized.

There are numerous ways in which pre-computed information may be used togenerate CTC signals. For example, the pre-computed information might beused by the sequence processor 806 at runtime. As another alternative,the pre-computed information might be used by the core processor 802 atruntime. FIGS. 13A 13D depict flowcharts of several differentembodiments of generating CTC signals. Each of these processes isperformed in the operational phase.

FIG. 13A depicts a flowchart of a process 1300 of generating CTC signalsthat may be used without pre-computing information for generating CTCsignals. This process could be used for a segment of a memory commandfor which there is adequate time to compute the information in realtime, for example.

Step 1302 includes the sequence processor 806 computing conditions for asub-clock of a memory operation. Computing the conditions may be basedon a combination of modes (or sub-modes), parameters, and/or statedependent bits. As noted, this may be performed at runtime, in responseto receiving a request to perform the memory operation.

Step 1304 includes the sequence processor 806 forming a packet 1100containing the conditions. In one embodiment, the conditions are placedin the condition bit map 1110 of the packet 1100. Step 1304 alsoincludes the sequence processor 806 providing the packet to the commandFIFO 922.

Step 1306 includes the core processor 802 accessing the packet 1100.FIFO manager 924 may provide the packet 1100 to the core processor 802.Step 1306 also includes the core processor 802 decoding the packet.

Step 1308 includes the core processor 802 generating CTC signals basedon the conditions in the packet. Further details of one embodiment ofthe core processor 802 generating CTC signals based on the conditions inthe packet are discussed below in connection with FIG. 15.

FIG. 13B depicts a flowchart of a process 1320 of generating CTC signalsthat may be used in conjunction with pre-computing conditions, such asthe conditions in the condition bit map 1110. Thus, prior to performingprocess 1320, the sequence processor 806 computes the conditions, whichare cached. The conditions may be cached in, for example, CTC cache 938a. In one embodiment, the conditions are pre-computed and cached duringa power on phase. In one embodiment, the conditions are pre-computed andcached during an operational phase. The process 1320 may be used for asegment of a memory command for which there is not adequate time for thesequence processor 806 to compute the conditions in real time. Even ifthere is adequate time for the sequence processor 806 to compute theconditions in real time the process 1320 could be performed to savepower.

Step 1322 includes the sequence processor 806 accessing the cachedconditions for the sub-clock of the memory operation. For example, thesequence processor 806 accesses the conditions from CTC cache 938 a.

Step 1324 includes the sequence processor 806 forming a packet 1100containing the cached conditions. In one embodiment, the conditions areplaced in the condition bit map 1110 of the packet 1100. Step 1324 alsoincludes the sequence processor 806 providing the packet to the commandFIFO 922.

Step 1326 includes the core processor 802 accessing the packet 1100.FIFO manager 924 may provide the packet 1100 to the core processor 802.Step 1326 also includes the core processor 802 decoding the packet.

Step 1328 includes the core processor 802 generating CTC signals basedon the conditions in the packet. Further details of one embodiment ofthe core processor 802 generating CTC signals based on the conditions inthe packet are discussed below in connection with FIG. 15.

FIG. 13C depicts a flowchart of a process 1340 of generating CTC signalsthat may be used in conjunction with pre-computing conditions, such asthe conditions in the condition bit map 1110. Thus, prior to performingprocess 1340, the sequence processor 806 computes the conditions, whichare cached. The conditions may be cached in, for example, CTC cache 938b. In one embodiment, the conditions are pre-computed and cached duringa power on phase. In one embodiment, the conditions are pre-computed andcached during an operational phase. The process 1340 may be used for asegment of a memory command for which there is not adequate time for thesequence processor 806 to compute the conditions in real time. Even ifthere is adequate time for the sequence processor 806 to compute theconditions in real time the process 1340 could be performed to savepower.

Step 1342 includes the sequence processor 806 forming a packet 1100containing a UC flag 1114 that is set to indicate that the coreprocessor 802 should access the cached conditions. Step 1342 alsoincludes the sequence processor 806 providing the packet to the commandFIFO 922.

Step 1344 includes the core processor 802 accessing the packet 1100.FIFO manager 924 may provide the packet 1100 to the core processor 802.Step 1344 also includes the core processor 802 decoding the packet.

Step 1346 includes the core processor 802 accessing the cachedconditions for the sub-clock of the memory operation. For example, thecore processor 802 accesses the conditions from CTC cache 938 b.

Step 1348 includes the core processor 802 generating CTC signals basedon the cached conditions. Further details of one embodiment of the coreprocessor 802 generating CTC signals based on the conditions in thepacket are discussed below in connection with FIG. 15.

In some embodiments, rather than caching the conditions, set/resetinformation that specifies when voltages to be applied to thenon-volatile memory structure are to be set or reset may be pre-computedand stored. This set/reset information could contain the information inthe CTC signal 1002 depicted in FIG. 10A. Thus, the CTC signal could bedirectly generated from the set/reset information. FIG. 13D depicts aflowchart of a process 1360 of generating CTC signals that may be usedin conjunction with pre-computing set/reset information. Thus, prior toperforming process 1360, the set/reset information is computed andcached. The set/reset information may be cached in, for example, CTCcache 938 b. In one embodiment, the set/reset information ispre-computed and cached during a power on phase. In one embodiment, theset/reset information is pre-computed and cached during an operationalphase. The process 1360 may be used for a segment of a memory commandfor which there is not adequate time for the sequence processor 806 tocompute the conditions in real time. Even if there is adequate time forthe sequence processor 806 to compute the conditions in real time theprocess 1360 could be performed to save power.

Step 1362 includes the sequence processor 806 forming a packet 1100containing a UC flag 1114 that is set to indicate that the coreprocessor 802 should access the cached set/reset information. Step 1362also includes the sequence processor 806 providing the packet to thecommand FIFO 922.

Step 1364 includes the core processor 802 accessing the packet 1100.FIFO manager 924 may provide the packet 1100 to the core processor 802.Step 1364 also includes the core processor 802 decoding the packet.

Step 1366 includes the core processor 802 accessing the cached set/resetinformation for the sub-clock of the memory operation. For example, thecore processor 802 accesses the set/reset information from CTC cache 938b.

Step 1368 includes the core processor 802 generating CTC signals basedon the cached conditions. For example, the core processor 802 maygenerated an electrical signal from the cached set/reset information.The electrical signal may be transmitted to the memory structure 126.

FIGS. 14A-14C depict details of embodiments of processing during runtimeby the sequence processor 806. FIG. 14C, to be discussed after firstdiscussing FIGS. 14A and 14B, depicts one embodiment of how storedconditions may be used at runtime by the sequence processor 806. FIG.14A is a flowchart of one embodiment of a command level flow for thesequence processor 806. In step 1402, sequence processor 806 is waitingto receive a new command. In one embodiment, the new command has anaddress. In step 1404, Sequencer Processor 806 uses the address receivedto lookup a pointer to execution code. In step 1406, Sequencer Processor806 executes the execution code (software/firmware) pointed to by thepointer.

FIG. 14B is a flowchart of one embodiment of a process of executing acommand on sequence processor 806. That is, the process of FIG. 14B isone example implementation of step 1406 of FIG. 14A. In step 1430,sequence processor 806 updates conditions. These are parameters thatsuch as reference voltages, mode of operation, etc. Based on theseconditions and the current command being performed, step 1432 includesupdating some of the bits of the Condition Bit Map 1110 of commandpacket 1100. In step 1434, sequence processor 806 triggers parametermanager 906 to update the parameters used for the current command (viaparameter control signal 934). In step 1436, sequence processor 806 setsthe system to be on the first sub-clock of the main clock for thecurrent command. In step 1438, sequence processor 806 implements thesequence for the current sub-clock. If the current sub-clock is the lastmain clock (step 1440) for the current command, then the process of FIG.14B is completed (step 1442). However, if the current main clock is notthe last main clock for the current command (step 1440), then theprocess of FIG. 14B continues at step 1406 with system set to the nextmain clock for the current command.

FIG. 14C is a flowchart of one embodiment of a sub-clock flow performedby sequence processor 806. That is, the process of FIG. 14C is oneexample implementation of step 1438 of FIG. 14B. In step 1470, the indexthat indicates the current sub-clock (e.g., Sub_clk) is set to 1. Instep 1472, configuration information for the current sub-clock isloaded. The sub-clock flow performed by Sequencer Processor 806 includedcalculating many conditions used to determine the control signals forthe memory structure. Step 1474 includes determining whether theconditions should be computed now, or accessed from storage.

If the conditions are to be computed now, then the sequence processor806 executes instructions to compute the conditions. Using the sequenceprocessor 806 to calculate the parameter/condition (step 1476) is likelyto take multiple clock cycles.

If the conditions are to accessed from storage, then the sequenceprocessor 806 accesses the conditions from storage in step 1478. Forexample, sequence processor 806 accesses the conditions from CTC cache938 a. The conditions may be accessed from storage in as little as oneclock cycle. Hence, many clock cycles may be saved by accessing theconditions from storage, relative to computing the conditions.

In step 1480, sequence processor 806 builds the command packet 1100 byinserting the bits into the Condition Bit Map of the command packet1100. In step 1482, command packet 1100 is sent from sequence processor806 to CMD FIFO 922, where it is accessed by FIFO manager 924 fordistribution to core processor 802 so that the conditions in commandpacket 1100 can be used by core processor 802 to generate the controlsignals to operate non-volatile memory structure 126. If there are morecommand packets to send for the current sub-clock (step 1484), then theprocess of FIG. 14C continues at step 1486. Step 1486 is to incrementthe sub-clock index. Then, control passes to step 1472. If there are nomore command packets to send for the current sub-clock (step 1484), thenthe process of FIG. 14C is completed at step 1488.

As noted above, in some embodiments, the core processor 802 may accessstored pre-computed information in order to save time and/or power. Thestored pre-computed information may be used by the core processor 802 togenerate CTC signals. FIG. 15 is a flowchart of one embodiment of aprocess 1500 of processing a packet 1100 in order to generate CTCsignals. The process 1500 may be performed for one segment (e.g.,sub-clock) of a memory operation. The process 1500 is performed by MCU112, in one embodiment. The process 1500 is performed by core processor802, in one embodiment. Reference will be made to the packet 1100 inFIG. 11A, but process 1500 is not limited to the packet in FIG. 11A.

Step 1502 includes accessing a packet from the CMD FIFO queue 922. Insome cases, the packet is for a segment for which pre-computedinformation is not accessed. In this case, the packet may containcondition bit map 1110 to indicate conditions, which may have beencomputed by the sequence processor 806. The conditions may have beendetermined by the sequence processor 806 in real time. Note that thisoption refers to a memory operation (or segment thereof) in which storepre-computed conditions are not being used. In some cases, the packet isfor a segment for which pre-computed information is accessed. In thiscase, the packet need not contain a valid condition bit map 1110.

Step 1504 is a determination of whether to use cached Set/Resetinformation to generate CTC signals or to generate the CTC signals basedon conditions specified in the packet. In one embodiment, the packet1100 comprises a UC flag 1114 that indicates whether the Set/Resetinformation should be accessed from the storage.

In the event that the cached Set/Reset information is not to be used,then control passes to step 1506. Step 1506 includes determining whichconditions are applicable for the group of CTC signals for a segment ofthe memory operation. Step 1506 includes determining which of theconditions will impact the CTC signals needed for the sub-clock of thememory operation. In one embodiment, the MCU 112 stores a local staticbit map that indicates which conditions will impact the CTC signalsneeded for the sub-clock of the memory operation. In one embodiment, theMCU 112 stores a local static bit map for each sub-clock. In oneembodiment, the core processor uses the data in the sub-clock field 1104of the packet 1100 to access a specific local static bit map for thatsub-clock. In one embodiment, the core processor compares (e.g.,performs a logical AND) between the conditions 1110 in the packet 1100and the local static bit map to determine which of the conditions 1110in the packet 1100 will impact the CTC signals.

Step 1508 includes setting or resetting CTC signals based on theconditions. In one embodiment, the MCU 112 has a set/reset array that asa Set bit and a Reset bit for each control signal. In one embodiment,the core processor either sets or resets the bits in the set/reset arraybased on the result of step 1506. In one embodiment, the core processorwrites a “1” to the set bit for a control signal to indicate that thecontrol signal should be set (e.g., move from a low value to a highvalue) for this sub-clock. If the control signal is not to be set, thenthe value of the set bit is “0”. In one embodiment, the core processorwrites a “1” to the reset bit for a control signal to indicate that thecontrol signal should be reset (e.g., move from a high value to a lowvalue) for this sub-clock. If the control signal is not to be reset,then the value of the reset bit is “0”.

Step 1510 also includes issuing the CTC signals to the memory structure126 to control the memory operation for this sub-clock. Step 1510 mayinclude forming CTC signals from the Set/Reset information. Step 1510may include examining the set/reset array for any bits having a value of“1”, which indicates that the corresponding control signal should eitherbe set or reset this sub-clock.

Step 1512 is performed when cached Set/Reset information is to be used(step 1504 is true). Step 1512 includes accessing cached Set/Resetinformation from storage. In one embodiment, the core processor 802accesses the Set/Reset information from CTC cache 938 b. In oneembodiment, the cached Set/Reset information for this sub-clock issimilar to the Set/Reset array discussed in connection with step 1508.Thus, rather than computing the Set/Reset array in steps 1506-1508 basedon the conditions 1110 in the packet 1100, the Set/Reset information maysimply be accessed. Accessing the Set/Reset information may take aslittle as one clock cycle. In contrast, steps 1506-1508 may takemultiple clock cycles.

After step 1512, control passes to step 1510. Step 1510 includes formingCTC signals from the Set/Reset information. Step 1510 also includesissuing the CTC signals to the memory structure 126 to control thememory operation for this sub-clock.

In some cases, there may be dynamic conditions that may affect the CTCsignals. A dynamic condition refers to a condition that can only bedetermined at runtime. An example of a dynamic condition is operatingtemperature. Runtime refers to the time after the power on phase whenrequests to perform memory operations are received by the MCU 112.Therefore, in one embodiment, a dynamic condition cannot be factored into the pre-computation of the conditions that are determined at, forexample, power on. However, the pre-computed conditions may be modifiedbased on the dynamic condition. In one embodiment, the MCU 112determines one or more dynamic conditions at runtime. In one embodiment,the MCU 112 determines at least one of the dynamic conditions after thememory operation for which CTC signals are to be generated is received.In one embodiment, the MCU 112 generates the CTC signals based on thecached information and further on the one or more dynamic conditions.For example, with reference to FIG. 13A, the sequence processor 806 maymodify one or more bits in the pre-computed conditions that wereaccessed in step 1322 based on the one or more dynamic conditions.Although this may slightly increase the time to perform step 1322,considerable time may be saved relative to performing the entirecomputation at runtime. Other techniques may be used to use dynamicconditions to impact the generation of the CTC signals. In oneembodiment, the core processor 802 accesses the cached conditions andmodifies one or more bits in the cached conditions based on the one ormore dynamic conditions.

Accordingly, it can be seen that, in a first embodiment, an apparatus isprovided that includes a memory structure comprising non-volatile memorycells and a control circuit connected to the memory structure. Thecontrol circuit is configured to generate and apply control signals tothe memory structure to perform memory operations. The control circuitcomprises a microcontroller configured to execute instructions todetermine information for generating the control signals for a type ofmemory operation prior to receiving a request to perform a memoryoperation of the type of memory operation. The microcontroller isconfigured to cache the information for the type of memory operation.The microcontroller is configured to access the information and generatethe control signals based on the cached information in response toreceiving a request to perform a memory operation of the type of memoryoperation. The microcontroller is configured to apply the controlsignals generated based on the cached information to the memorystructure to perform the memory operation.

In a second embodiment, in furtherance to of the first embodiment, theinformation comprises conditions that are relevant for the non-volatilememory structure and from which the control signals for the type ofmemory operation are derivable. The cached information comprises cachedconditions that are relevant for the non-volatile memory structure.

In a third embodiment, in furtherance to any of the first to secondembodiments, the microcontroller is further configured to determine,after receiving the request, the control signals based on the cachedconditions and information that is specific to the type of memoryoperation.

In a fourth embodiment, in furtherance to any of the first to thirdembodiments, the microcontroller comprises a first processor configuredto execute a first set of instructions to form a packet that contains aflag that indicates the cached conditions are to be accessed. Themicrocontroller comprises a second processor configured to execute asecond set of instructions to access the packet. The second processor isconfigured to execute the second set of instructions to access thecached conditions and to generate the control signals based on thecached conditions.

In a fifth embodiment, in furtherance to any of the first to fourthembodiments, the microcontroller comprises a first processor configuredto execute a first set of instructions to access the cached conditions.The first processor is configured to execute the first set ofinstructions to form a packet that contains the cached conditions. Themicrocontroller comprises a second processor configured to execute asecond set of instructions to access the packet. The second processor isconfigured to execute the second set of instructions to generate thecontrol signals based on the conditions in the packet.

In a sixth embodiment, in furtherance to any of the first to fifthembodiments, the information comprises set/reset information thatspecifies when the control signals are to be set or reset. The cachedinformation comprises cached set/reset information.

In a seventh embodiment, in furtherance to any of the first to sixthembodiments, the microcontroller is further configured to apply thecontrol signals to control the non-volatile memory structure based onthe cached set/reset information.

In an eighth embodiment, in furtherance to any of the first to seventhembodiments, the microcontroller comprises a first processor configuredto execute a first set of instructions to form a packet that contains aflag that indicates the cached set/reset information is to be accessed.The microcontroller comprises a second processor configured to execute asecond set of instructions to access the packet. The second processor isconfigured to execute the second set of instructions to access thecached set/reset information and to generate the control signals basedon the cached set/reset information.

In a ninth embodiment, in furtherance to any of the first to eighthembodiments, the microcontroller is further configured to execute theinstructions during a power on phase of the non-volatile storageapparatus to determine the information for generating the controlsignals for the type of memory operation.

In a tenth embodiment, in furtherance to the any of the first to ninthembodiments, the microcontroller is further configured to access storedparameters during a power on phase of the non-volatile storageapparatus. The microcontroller is further configured to execute theinstructions during the power on phase to determine the information forgenerating the control signals for the type of memory operation based onthe stored parameters.

In an eleventh embodiment, in furtherance to any of the first to tenthembodiments, the microcontroller is further configured to determine adynamic condition after the memory operation is received. Themicrocontroller is further configured to generate the control signalsbased on the cached information and further on the dynamic condition.

Accordingly, it can be seen that one embodiment includes a method ofoperating a non-volatile memory system. The method comprises accessingparameters from storage in the non-volatile memory system. The methodcomprises executing instructions on a processor in the non-volatilememory system to compute information that is applicable to core timingcontrol signals to be applied to a non-volatile memory structure in thenon-volatile memory system during a segment of a memory operation,including using the parameters to compute the information prior to thenon-volatile memory system receiving a request to perform the memoryoperation. The method comprises storing the computed information instorage in the non-volatile memory system. The method comprisesaccessing the stored information in response to receiving a request toperform the memory operation. The method comprises setting or resettingone or more core timing control signals based on the stored information.The method comprises using the core timing control signals to controlthe non-volatile memory structure during the segment of the memoryoperation.

Accordingly, it can be seen that one embodiment includes a non-volatilestorage system. The non-volatile storage system comprises a memory diecomprising a control circuit and a memory structure comprisingnon-volatile memory cells. The control circuit is configured to generateand apply a set of control signals to control the memory structure toperform memory operations. The control circuit comprises a firstprocessor configured to execute first instructions to compute conditionsfor a segment of a memory operation. The control circuit comprises asecond processor configured to execute second instructions to generatecontrol signals for the segment of the memory operation based on theconditions. The first processor is configured to pre-compute theconditions for the segment of the memory operation prior to receiving arequest to perform the memory operation, wherein the control circuit isconfigured to store the pre-computed conditions. The control circuit isconfigured to access the stored pre-computed conditions in response toreceiving a request to perform the memory operation. The secondprocessor is configured to execute the second instructions generate thecontrol signals for the segment of the memory operation based on thestored pre-computed conditions.

For purposes of this document, reference in the specification to “anembodiment,” “one embodiment,” “some embodiments,” or “anotherembodiment” may be used to describe different embodiments or the sameembodiment.

For purposes of this document, a connection may be a direct connectionor an indirect connection (e.g., via one or more others parts). In somecases, when an element is referred to as being connected or coupled toanother element, the element may be directly connected to the otherelement or indirectly connected to the other element via interveningelements. When an element is referred to as being directly connected toanother element, then there are no intervening elements between theelement and the other element. Two devices are “in communication” ifthey are directly or indirectly connected so that they can communicateelectronic signals between them.

For purposes of this document, the term “based on” may be read as “basedat least in part on.”

For purposes of this document, without additional context, use ofnumerical terms such as a “first” object, a “second” object, and a“third” object may not imply an ordering of objects, but may instead beused for identification purposes to identify different objects.

For purposes of this document, the term “set” of objects may refer to a“set” of one or more of the objects.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit to the precise form disclosed. Many modifications and variationsare possible in light of the above teaching. The described embodimentswere chosen in order to best explain the principles of the proposedtechnology and its practical application, to thereby enable othersskilled in the art to best utilize it in various embodiments and withvarious modifications as are suited to the particular use contemplated.It is intended that the scope be defined by the claims appended hereto.

1. An apparatus, comprising: a control circuit configured to beconnected to a memory structure comprising non-volatile memory cells,the control circuit comprising a microcontroller configured to:determine information for generating control signals for a type ofmemory operation prior to receiving a request to perform a memoryoperation of the type of memory operation in the memory structure; storethe information for the type of memory operation; generate the controlsignals based on the stored information in response to receiving arequest to perform a memory operation of the type of memory operation;and use the control signals generated based on the stored information tocontrol at least one segment of the memory operation in the memorystructure.
 2. The apparatus of claim 1, wherein the informationcomprises: conditions that are relevant for the memory structure andfrom which the control signals for the type of memory operation arederivable.
 3. The apparatus of claim 2, wherein the microcontroller isconfigured to determine the conditions based on one or more of: a modeand/or a sub-mode of the memory operation; one or more parameters thatspecify options to be applied during the memory operation; orinformation that specifies how the flow of the control signals for thememory operation is to proceed.
 4. The apparatus of claim 1, wherein themicrocontroller is further configured to: determine, after receiving therequest, the control signals based on the stored information andinformation that is specific to the type of memory operation.
 5. Theapparatus of claim 1, wherein the microcontroller comprises: a firstprocessor configured, in response to the request to perform the memoryoperation, to execute a first set of instructions to form a packet thatcontains a flag that indicates the stored information is to be accessed;and a second processor configured to execute a second set ofinstructions to access the packet, the second processor configured toexecute the second set of instructions to access the stored informationin response to the flag being set and to generate the control signalsbased on the stored information.
 6. The apparatus of claim 1, whereinthe microcontroller comprises: a first processor configured to execute afirst set of instructions to access the stored information in responseto the request to perform the memory operation, the first processorconfigured to execute the first set of instructions to form a packetthat contains the stored information; and a second processor configuredto execute a second set of instructions to access the packet, the secondprocessor configured to execute the second set of instructions togenerate the control signals based on the information in the packet. 7.The apparatus of claim 1, wherein the information comprises: set/resetinformation that specifies a segment of the memory operation at whichthe control signals are to be set or reset, wherein the storedinformation comprises stored set/reset information.
 8. The apparatus ofclaim 7, wherein the microcontroller is further configured to: increasea voltage that is applied to a region of the memory structure at a firstsegment of the memory operation at which a first control signal of thecontrol signals is set; and decrease the voltage that is applied to theregion of the memory structure at a second segment of the memoryoperation at which the first control signal is reset.
 9. The apparatusof claim 7, wherein the microcontroller comprises: a first processorconfigured to execute a first set of instructions to form a packet thatcontains a flag that indicates the stored set/reset information is to beaccessed; and a second processor configured to execute a second set ofinstructions to access the packet, the second processor configured toexecute the second set of instructions to access the stored set/resetinformation and to generate the control signals based on the storedset/reset information.
 10. The apparatus of claim 1, wherein themicrocontroller is further configured to: determine the information forgenerating the control signals for the type of memory operation during apower on phase of the apparatus.
 11. A method, comprising: executinginstructions on a processor to compute information associated with coretiming control signals that control a memory operation in a non-volatilememory structure; storing the computed information in storage that isaccessible to the processor; accessing the stored information inresponse to the processor receiving a request to perform the memoryoperation; setting or resetting one or more core timing control signalsbased on the stored information; and using the core timing controlsignals to control the non-volatile memory structure during the memoryoperation.
 12. The method of claim 11, wherein executing instructions onthe processor to compute the information associated with the core timingcontrol signals comprises: computing the information based on a modeand/or a sub-mode of the memory operation.
 13. The method of claim 12,wherein executing instructions on the processor to compute theinformation associated with the core timing control signals furthercomprises: computing the information based on parameters that specifyoptions to be applied during the memory operation.
 14. The method ofclaim 13, wherein executing instructions on the processor to compute theinformation associated with the core timing control signals furthercomprises: computing the information based on information that specifieshow the flow of the core timing control signals is to proceed.
 15. Themethod of claim 11, wherein executing instructions on the processor tocompute the information associated with the core timing control signalsfurther comprises: computing set/reset information that indicateswhether the one or more core timing control signals are to be set orreset for a segment of the memory operation.
 16. A non-volatile storagesystem, comprising: a die comprising a control circuit configured to beconnected to a memory structure comprising non-volatile memory cells,the control circuit configured to generate and apply a set of controlsignals to control the memory structure to perform memory operations,the control circuit comprising: a first processor configured to executefirst instructions to compute conditions for a sub-clock of a memoryoperation; and a second processor configured to execute secondinstructions to generate control signals for the sub-clock of the memoryoperation based on the conditions; wherein the first processor isconfigured to pre-compute the conditions for the sub-clock of the memoryoperation prior to receiving a request from a memory controller toperform the memory operation, wherein the first processor or the secondprocessor stores the pre-computed conditions; wherein the controlcircuit is configured to use the stored pre-computed conditions togenerate the control signals for the sub-clock of the memory operationby at least one of: the first processor accessing the storedpre-computed conditions for the sub-clock of the memory operation inresponse to the first processor receiving a request from the memorycontroller to perform the memory operation, the first processorproviding the stored conditions to the second processor; or the secondprocessor accessing the stored pre-computed conditions in response to arequest from the first processor to access the stored pre-computedconditions, wherein the first processor requests the second processor toaccess the stored pre-computed conditions in response to the firstprocessor receiving a request from the memory controller to perform thememory operation.
 17. The non-volatile storage system of claim 16,wherein: the first processor is configured to form a packet having aflag indicating that the second processor is to access the storedpre-computed conditions, wherein the first processor forms the packet inresponse to a request from the memory controller to perform the memoryoperation; the second processor is configured to decode the packet; thesecond processor is configured to access the stored pre-computedconditions; and the second processor is configured to generate thecontrol signals for the sub-clock based on the stored pre-computedconditions.
 18. The non-volatile storage system of claim 16, wherein:the first processor is configured to access the stored pre-computedconditions in response to the request from the memory controller toperform the memory operation; the first processor is configured to forma packet having the stored pre-computed conditions that were accessed inresponse to the request from the memory controller to perform the memoryoperation; the second processor is configured to decode the packet; andthe second processor is configured to generate the control signals forthe sub-clock of the memory operation based on the pre-computedconditions in the packet.
 19. The non-volatile storage system of claim16, wherein: the first processor is configured to pre-compute conditionsfor the sub-clock of the memory operation during a power on phase; andthe first processor is configured to store the pre-computed conditionsduring the power on phase.
 20. The non-volatile storage system of claim16, wherein: the first processor is configured to pre-compute conditionsfor the sub-clock of the memory operation during a power on phase; andthe first processor is configured to instruct the second processor tostore the pre-computed conditions during the power on phase.